43 typedef unsigned char byte;
44 typedef unsigned short word;
45 typedef unsigned long int dword;
50 #define SMC_IO_EXTENT 16
73 #define BANK_SELECT 14
77 #define TCR_REG 0x0000 // transmit control register
78 #define TCR_ENABLE 0x0001 // When 1 we can transmit
79 #define TCR_LOOP 0x0002 // Controls output pin LBK
80 #define TCR_FORCOL 0x0004 // When 1 will force a collision
81 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
82 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
83 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
84 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
85 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
86 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
87 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
92 #define TCR_DEFAULT TCR_ENABLE
97 #define EPH_STATUS_REG 0x0002
98 #define ES_TX_SUC 0x0001 // Last TX was successful
99 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
100 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
101 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
102 #define ES_16COL 0x0010 // 16 Collisions Reached
103 #define ES_SQET 0x0020 // Signal Quality Error Test
104 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
105 #define ES_TXDEFR 0x0080 // Transmit Deferred
106 #define ES_LATCOL 0x0200 // Late collision detected on last tx
107 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
108 #define ES_EXC_DEF 0x0800 // Excessive Deferral
109 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
110 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
111 #define ES_TXUNRN 0x8000 // Tx Underrun
116 #define RCR_REG 0x0004
117 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
118 #define RCR_PRMS 0x0002 // Enable promiscuous mode
119 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
120 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
121 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
122 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
123 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
124 #define RCR_SOFTRST 0x8000 // resets the chip
127 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
128 #define RCR_CLEAR 0x0 // set it to a base state
132 #define COUNTER_REG 0x0006
136 #define MIR_REG 0x0008
140 #define RPC_REG 0x000A
141 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
142 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
143 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
144 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
145 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
146 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
147 #define RPC_LED_RES (0x01) // LED = Reserved
148 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
149 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
150 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
151 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
152 #define RPC_LED_TX (0x06) // LED = TX packet occurred
153 #define RPC_LED_RX (0x07) // LED = RX packet occurred
154 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
160 #define BSR_REG 0x000E
165 #define CONFIG_REG 0x0000
166 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
167 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
168 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
169 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
172 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
177 #define BASE_REG 0x0002
182 #define ADDR0_REG 0x0004
183 #define ADDR1_REG 0x0006
184 #define ADDR2_REG 0x0008
189 #define GP_REG 0x000A
194 #define CTL_REG 0x000C
195 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
196 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
197 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
198 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
199 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
200 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
201 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
202 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
207 #define MMU_CMD_REG 0x0000
208 #define MC_BUSY 1 // When 1 the last release has not completed
209 #define MC_NOP (0<<5) // No Op
210 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
211 #define MC_RESET (2<<5) // Reset MMU to initial state
212 #define MC_REMOVE (3<<5) // Remove the current rx packet
213 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
214 #define MC_FREEPKT (5<<5) // Release packet in PNR register
215 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
216 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
221 #define PN_REG 0x0002
226 #define AR_REG 0x0003
227 #define AR_FAILED 0x80 // Alocation Failed
232 #define RXFIFO_REG 0x0004 // Must be read as a word
233 #define RXFIFO_REMPTY 0x8000 // RX FIFO Empty
238 #define TXFIFO_REG RXFIFO_REG // Must be read as a word
239 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
244 #define PTR_REG 0x0006
245 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
246 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
247 #define PTR_READ 0x2000 // When 1 the operation is a read
252 #define DATA_REG 0x0008
257 #define INT_REG 0x000C
262 #define IM_REG 0x000D
263 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
264 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
265 #define IM_EPH_INT 0x20 // Set by Etheret Protocol Handler section
266 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
267 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
268 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
269 #define IM_TX_INT 0x02 // Transmit Interrrupt
270 #define IM_RCV_INT 0x01 // Receive Interrupt
275 #define MCAST_REG1 0x0000
276 #define MCAST_REG2 0x0002
277 #define MCAST_REG3 0x0004
278 #define MCAST_REG4 0x0006
283 #define MII_REG 0x0008
284 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
285 #define MII_MDOE 0x0008 // MII Output Enable
286 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
287 #define MII_MDI 0x0002 // MII Input, pin MDI
288 #define MII_MDO 0x0001 // MII Output, pin MDO
293 #define REV_REG 0x000A
299 #define ERCV_REG 0x000C
300 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
301 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
305 #define EXT_REG 0x0000
313 #define CHIP_91100FD 8
314 #define CHIP_91111FD 9
316 static const char * chip_ids[ 15 ] = {
331 #define TS_SUCCESS 0x0001
332 #define TS_LOSTCAR 0x0400
333 #define TS_LATCOL 0x0200
334 #define TS_16COL 0x0010
339 #define RS_ALGNERR 0x8000
340 #define RS_BRODCAST 0x4000
341 #define RS_BADCRC 0x2000
342 #define RS_ODDFRAME 0x1000 // bug: the LAN91C111 never sets this on receive
343 #define RS_TOOLONG 0x0800
344 #define RS_TOOSHORT 0x0400
345 #define RS_MULTICAST 0x0001
346 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
359 #define PHY_CNTL_REG 0x00
360 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
361 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
362 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
363 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
364 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
365 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
366 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
367 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
368 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
371 #define PHY_STAT_REG 0x01
372 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
373 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
374 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
375 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
376 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
377 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
378 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
379 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
380 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
381 #define PHY_STAT_LINK 0x0004 // 1=valid link
382 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
383 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
386 #define PHY_ID1_REG 0x02 // PHY Identifier 1
387 #define PHY_ID2_REG 0x03 // PHY Identifier 2
390 #define PHY_AD_REG 0x04
391 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
392 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
393 #define PHY_AD_RF 0x2000 // 1=advertise remote fault
394 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
395 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
396 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
397 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
398 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
399 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
402 #define PHY_RMT_REG 0x05
406 #define PHY_CFG1_REG 0x10
407 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
408 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
409 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
410 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
411 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
412 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
413 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
414 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
415 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
416 #define PHY_CFG1_TLVL_MASK 0x003C
417 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
421 #define PHY_CFG2_REG 0x11
422 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
423 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
424 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
425 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
428 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
429 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
430 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
431 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
432 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
433 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
434 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
435 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
436 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
437 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
438 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
441 #define PHY_MASK_REG 0x13 // Interrupt Mask
453 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
456 #define SMC_ENABLE_INT(x) {\
459 mask = inb( ioaddr + IM_REG );\
461 outb( mask, ioaddr + IM_REG ); \
466 #define SMC_DISABLE_INT(x) {\
469 mask = inb( ioaddr + IM_REG );\
471 outb( mask, ioaddr + IM_REG ); \
483 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
496 #define CTL_SMC (CTL_BUS+1389) // arbitrary and hopefully unused
562 #endif // CONFIG_SYSCTL