29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
32 #define E1000_TXD_POPTS_IXSM 0x01
33 #define E1000_TXD_POPTS_TXSM 0x02
34 #define E1000_TXD_CMD_EOP 0x01000000
35 #define E1000_TXD_CMD_IFCS 0x02000000
36 #define E1000_TXD_CMD_IC 0x04000000
37 #define E1000_TXD_CMD_RS 0x08000000
38 #define E1000_TXD_CMD_RPS 0x10000000
39 #define E1000_TXD_CMD_DEXT 0x20000000
40 #define E1000_TXD_CMD_VLE 0x40000000
41 #define E1000_TXD_CMD_IDE 0x80000000
42 #define E1000_TXD_STAT_DD 0x00000001
43 #define E1000_TXD_STAT_EC 0x00000002
44 #define E1000_TXD_STAT_LC 0x00000004
45 #define E1000_TXD_STAT_TU 0x00000008
46 #define E1000_TXD_CMD_TCP 0x01000000
47 #define E1000_TXD_CMD_IP 0x02000000
48 #define E1000_TXD_CMD_TSE 0x04000000
49 #define E1000_TXD_STAT_TC 0x00000004
52 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
53 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
57 #define E1000_WUC_APME 0x00000001
58 #define E1000_WUC_PME_EN 0x00000002
59 #define E1000_WUC_PHY_WAKE 0x00000100
62 #define E1000_WUFC_LNKC 0x00000001
63 #define E1000_WUFC_MAG 0x00000002
64 #define E1000_WUFC_EX 0x00000004
65 #define E1000_WUFC_MC 0x00000008
66 #define E1000_WUFC_BC 0x00000010
67 #define E1000_WUFC_ARP 0x00000020
70 #define E1000_WUS_LNKC E1000_WUFC_LNKC
71 #define E1000_WUS_MAG E1000_WUFC_MAG
72 #define E1000_WUS_EX E1000_WUFC_EX
73 #define E1000_WUS_MC E1000_WUFC_MC
74 #define E1000_WUS_BC E1000_WUFC_BC
77 #define E1000_CTRL_EXT_LPCD 0x00000004
78 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080
79 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000004
80 #define E1000_CTRL_EXT_EE_RST 0x00002000
81 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000
82 #define E1000_CTRL_EXT_RO_DIS 0x00020000
83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000
84 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
85 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
86 #define E1000_CTRL_EXT_EIAME 0x01000000
87 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
88 #define E1000_CTRL_EXT_IAME 0x08000000
89 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000
90 #define E1000_CTRL_EXT_PBA_CLR 0x80000000
91 #define E1000_CTRL_EXT_LSECCK 0x00001000
92 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
95 #define E1000_RXD_STAT_DD 0x01
96 #define E1000_RXD_STAT_EOP 0x02
97 #define E1000_RXD_STAT_IXSM 0x04
98 #define E1000_RXD_STAT_VP 0x08
99 #define E1000_RXD_STAT_UDPCS 0x10
100 #define E1000_RXD_STAT_TCPCS 0x20
101 #define E1000_RXD_ERR_CE 0x01
102 #define E1000_RXD_ERR_SE 0x02
103 #define E1000_RXD_ERR_SEQ 0x04
104 #define E1000_RXD_ERR_CXE 0x10
105 #define E1000_RXD_ERR_TCPE 0x20
106 #define E1000_RXD_ERR_RXE 0x80
107 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF
109 #define E1000_RXDEXT_STATERR_CE 0x01000000
110 #define E1000_RXDEXT_STATERR_SE 0x02000000
111 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
112 #define E1000_RXDEXT_STATERR_CXE 0x10000000
113 #define E1000_RXDEXT_STATERR_RXE 0x80000000
116 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
119 E1000_RXD_ERR_SEQ | \
120 E1000_RXD_ERR_CXE | \
124 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
125 E1000_RXDEXT_STATERR_CE | \
126 E1000_RXDEXT_STATERR_SE | \
127 E1000_RXDEXT_STATERR_SEQ | \
128 E1000_RXDEXT_STATERR_CXE | \
129 E1000_RXDEXT_STATERR_RXE)
131 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
134 #define E1000_MANC_SMBUS_EN 0x00000001
135 #define E1000_MANC_ASF_EN 0x00000002
136 #define E1000_MANC_ARP_EN 0x00002000
137 #define E1000_MANC_RCV_TCO_EN 0x00020000
138 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
140 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
142 #define E1000_MANC_EN_MNG2HOST 0x00200000
144 #define E1000_MANC2H_PORT_623 0x00000020
145 #define E1000_MANC2H_PORT_664 0x00000040
146 #define E1000_MDEF_PORT_623 0x00000800
147 #define E1000_MDEF_PORT_664 0x00000400
150 #define E1000_RCTL_EN 0x00000002
151 #define E1000_RCTL_SBP 0x00000004
152 #define E1000_RCTL_UPE 0x00000008
153 #define E1000_RCTL_MPE 0x00000010
154 #define E1000_RCTL_LPE 0x00000020
155 #define E1000_RCTL_LBM_NO 0x00000000
156 #define E1000_RCTL_LBM_MAC 0x00000040
157 #define E1000_RCTL_LBM_TCVR 0x000000C0
158 #define E1000_RCTL_DTYP_PS 0x00000400
159 #define E1000_RCTL_RDMTS_HALF 0x00000000
160 #define E1000_RCTL_MO_SHIFT 12
161 #define E1000_RCTL_MO_3 0x00003000
162 #define E1000_RCTL_BAM 0x00008000
164 #define E1000_RCTL_SZ_2048 0x00000000
165 #define E1000_RCTL_SZ_1024 0x00010000
166 #define E1000_RCTL_SZ_512 0x00020000
167 #define E1000_RCTL_SZ_256 0x00030000
169 #define E1000_RCTL_SZ_16384 0x00010000
170 #define E1000_RCTL_SZ_8192 0x00020000
171 #define E1000_RCTL_SZ_4096 0x00030000
172 #define E1000_RCTL_VFE 0x00040000
173 #define E1000_RCTL_CFIEN 0x00080000
174 #define E1000_RCTL_CFI 0x00100000
175 #define E1000_RCTL_PMCF 0x00800000
176 #define E1000_RCTL_BSEX 0x02000000
177 #define E1000_RCTL_SECRC 0x04000000
196 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
197 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
198 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
199 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
201 #define E1000_PSRCTL_BSIZE0_SHIFT 7
202 #define E1000_PSRCTL_BSIZE1_SHIFT 2
203 #define E1000_PSRCTL_BSIZE2_SHIFT 6
204 #define E1000_PSRCTL_BSIZE3_SHIFT 14
207 #define E1000_SWFW_EEP_SM 0x1
208 #define E1000_SWFW_PHY0_SM 0x2
209 #define E1000_SWFW_PHY1_SM 0x4
210 #define E1000_SWFW_CSR_SM 0x8
213 #define E1000_CTRL_FD 0x00000001
214 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
215 #define E1000_CTRL_LRST 0x00000008
216 #define E1000_CTRL_ASDE 0x00000020
217 #define E1000_CTRL_SLU 0x00000040
218 #define E1000_CTRL_ILOS 0x00000080
219 #define E1000_CTRL_SPD_SEL 0x00000300
220 #define E1000_CTRL_SPD_10 0x00000000
221 #define E1000_CTRL_SPD_100 0x00000100
222 #define E1000_CTRL_SPD_1000 0x00000200
223 #define E1000_CTRL_FRCSPD 0x00000800
224 #define E1000_CTRL_FRCDPX 0x00001000
225 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000
226 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000
227 #define E1000_CTRL_SWDPIN0 0x00040000
228 #define E1000_CTRL_SWDPIN1 0x00080000
229 #define E1000_CTRL_SWDPIO0 0x00400000
230 #define E1000_CTRL_RST 0x04000000
231 #define E1000_CTRL_RFCE 0x08000000
232 #define E1000_CTRL_TFCE 0x10000000
233 #define E1000_CTRL_VME 0x40000000
234 #define E1000_CTRL_PHY_RST 0x80000000
242 #define E1000_STATUS_FD 0x00000001
243 #define E1000_STATUS_LU 0x00000002
244 #define E1000_STATUS_FUNC_MASK 0x0000000C
245 #define E1000_STATUS_FUNC_SHIFT 2
246 #define E1000_STATUS_FUNC_1 0x00000004
247 #define E1000_STATUS_TXOFF 0x00000010
248 #define E1000_STATUS_SPEED_10 0x00000000
249 #define E1000_STATUS_SPEED_100 0x00000040
250 #define E1000_STATUS_SPEED_1000 0x00000080
251 #define E1000_STATUS_LAN_INIT_DONE 0x00000200
252 #define E1000_STATUS_PHYRA 0x00000400
253 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
257 #define HALF_DUPLEX 1
258 #define FULL_DUPLEX 2
261 #define ADVERTISE_10_HALF 0x0001
262 #define ADVERTISE_10_FULL 0x0002
263 #define ADVERTISE_100_HALF 0x0004
264 #define ADVERTISE_100_FULL 0x0008
265 #define ADVERTISE_1000_HALF 0x0010
266 #define ADVERTISE_1000_FULL 0x0020
269 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
270 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
272 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
273 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
274 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
275 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
276 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
278 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
281 #define E1000_PHY_LED0_MODE_MASK 0x00000007
282 #define E1000_PHY_LED0_IVRT 0x00000008
283 #define E1000_PHY_LED0_MASK 0x0000001F
285 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
286 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
287 #define E1000_LEDCTL_LED0_IVRT 0x00000040
288 #define E1000_LEDCTL_LED0_BLINK 0x00000080
290 #define E1000_LEDCTL_MODE_LINK_UP 0x2
291 #define E1000_LEDCTL_MODE_LED_ON 0xE
292 #define E1000_LEDCTL_MODE_LED_OFF 0xF
295 #define E1000_TXD_DTYP_D 0x00100000
296 #define E1000_TXD_POPTS_IXSM 0x01
297 #define E1000_TXD_POPTS_TXSM 0x02
298 #define E1000_TXD_CMD_EOP 0x01000000
299 #define E1000_TXD_CMD_IFCS 0x02000000
300 #define E1000_TXD_CMD_IC 0x04000000
301 #define E1000_TXD_CMD_RS 0x08000000
302 #define E1000_TXD_CMD_RPS 0x10000000
303 #define E1000_TXD_CMD_DEXT 0x20000000
304 #define E1000_TXD_CMD_VLE 0x40000000
305 #define E1000_TXD_CMD_IDE 0x80000000
306 #define E1000_TXD_STAT_DD 0x00000001
307 #define E1000_TXD_STAT_EC 0x00000002
308 #define E1000_TXD_STAT_LC 0x00000004
309 #define E1000_TXD_STAT_TU 0x00000008
310 #define E1000_TXD_CMD_TCP 0x01000000
311 #define E1000_TXD_CMD_IP 0x02000000
312 #define E1000_TXD_CMD_TSE 0x04000000
313 #define E1000_TXD_STAT_TC 0x00000004
316 #define E1000_TCTL_EN 0x00000002
317 #define E1000_TCTL_PSP 0x00000008
318 #define E1000_TCTL_CT 0x00000ff0
319 #define E1000_TCTL_COLD 0x003ff000
320 #define E1000_TCTL_RTLC 0x01000000
321 #define E1000_TCTL_MULR 0x10000000
326 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
329 #define E1000_RXCSUM_TUOFL 0x00000200
330 #define E1000_RXCSUM_IPPCSE 0x00001000
333 #define E1000_RFCTL_NFSW_DIS 0x00000040
334 #define E1000_RFCTL_NFSR_DIS 0x00000080
335 #define E1000_RFCTL_ACK_DIS 0x00001000
336 #define E1000_RFCTL_EXTEN 0x00008000
337 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
338 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
341 #define E1000_COLLISION_THRESHOLD 15
342 #define E1000_CT_SHIFT 4
343 #define E1000_COLLISION_DISTANCE 63
344 #define E1000_COLD_SHIFT 12
347 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
349 #define E1000_TIPG_IPGT_MASK 0x000003FF
351 #define DEFAULT_82543_TIPG_IPGR1 8
352 #define E1000_TIPG_IPGR1_SHIFT 10
354 #define DEFAULT_82543_TIPG_IPGR2 6
355 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
356 #define E1000_TIPG_IPGR2_SHIFT 20
358 #define MAX_JUMBO_FRAME_SIZE 0x3F00
361 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
362 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
363 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
364 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
365 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
366 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
367 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
368 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
369 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
371 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
372 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
373 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
374 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
376 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
379 #define E1000_PBA_8K 0x0008
380 #define E1000_PBA_16K 0x0010
382 #define E1000_PBS_16K E1000_PBA_16K
388 #define MIN_NUM_XMITS 1000
391 #define E1000_SWSM_SMBI 0x00000001
392 #define E1000_SWSM_SWESMBI 0x00000002
393 #define E1000_SWSM_DRV_LOAD 0x00000008
395 #define E1000_SWSM2_LOCK 0x00000002
398 #define E1000_ICR_TXDW 0x00000001
399 #define E1000_ICR_LSC 0x00000004
400 #define E1000_ICR_RXSEQ 0x00000008
401 #define E1000_ICR_RXDMT0 0x00000010
402 #define E1000_ICR_RXT0 0x00000080
403 #define E1000_ICR_INT_ASSERTED 0x80000000
404 #define E1000_ICR_RXQ0 0x00100000
405 #define E1000_ICR_RXQ1 0x00200000
406 #define E1000_ICR_TXQ0 0x00400000
407 #define E1000_ICR_TXQ1 0x00800000
408 #define E1000_ICR_OTHER 0x01000000
411 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000
412 #define E1000_PBA_ECC_COUNTER_SHIFT 20
413 #define E1000_PBA_ECC_CORR_EN 0x00000001
414 #define E1000_PBA_ECC_STAT_CLR 0x00000002
415 #define E1000_PBA_ECC_INT_EN 0x00000004
426 #define IMS_ENABLE_MASK ( \
434 #define E1000_IMS_TXDW E1000_ICR_TXDW
435 #define E1000_IMS_LSC E1000_ICR_LSC
436 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
437 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
438 #define E1000_IMS_RXT0 E1000_ICR_RXT0
439 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0
440 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1
441 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0
442 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1
443 #define E1000_IMS_OTHER E1000_ICR_OTHER
446 #define E1000_ICS_LSC E1000_ICR_LSC
447 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
448 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
451 #define E1000_TXDCTL_PTHRESH 0x0000003F
452 #define E1000_TXDCTL_HTHRESH 0x00003F00
453 #define E1000_TXDCTL_WTHRESH 0x003F0000
454 #define E1000_TXDCTL_GRAN 0x01000000
455 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
456 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
458 #define E1000_TXDCTL_COUNT_DESC 0x00400000
461 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
462 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
463 #define FLOW_CONTROL_TYPE 0x8808
466 #define E1000_VLAN_FILTER_TBL_SIZE 128
476 #define E1000_RAR_ENTRIES 15
477 #define E1000_RAH_AV 0x80000000
478 #define E1000_RAL_MAC_ADDR_LEN 4
479 #define E1000_RAH_MAC_ADDR_LEN 2
482 #define E1000_ERR_NVM 1
483 #define E1000_ERR_PHY 2
484 #define E1000_ERR_CONFIG 3
485 #define E1000_ERR_PARAM 4
486 #define E1000_ERR_MAC_INIT 5
487 #define E1000_ERR_PHY_TYPE 6
488 #define E1000_ERR_RESET 9
489 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
490 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
491 #define E1000_BLK_PHY_RESET 12
492 #define E1000_ERR_SWFW_SYNC 13
493 #define E1000_NOT_IMPLEMENTED 14
494 #define E1000_ERR_INVALID_ARGUMENT 16
495 #define E1000_ERR_NO_SPACE 17
496 #define E1000_ERR_NVM_PBA_SECTION 18
499 #define FIBER_LINK_UP_LIMIT 50
500 #define COPPER_LINK_UP_LIMIT 10
501 #define PHY_AUTO_NEG_LIMIT 45
502 #define PHY_FORCE_LIMIT 20
504 #define MASTER_DISABLE_TIMEOUT 800
506 #define PHY_CFG_TIMEOUT 100
508 #define MDIO_OWNERSHIP_TIMEOUT 10
510 #define AUTO_READ_DONE_TIMEOUT 10
513 #define E1000_FCRTH_RTH 0x0000FFF8
514 #define E1000_FCRTL_RTL 0x0000FFF8
515 #define E1000_FCRTL_XONE 0x80000000
518 #define E1000_TXCW_FD 0x00000020
519 #define E1000_TXCW_PAUSE 0x00000080
520 #define E1000_TXCW_ASM_DIR 0x00000100
521 #define E1000_TXCW_PAUSE_MASK 0x00000180
522 #define E1000_TXCW_ANE 0x80000000
525 #define E1000_RXCW_CW 0x0000ffff
526 #define E1000_RXCW_IV 0x08000000
527 #define E1000_RXCW_C 0x20000000
528 #define E1000_RXCW_SYNCH 0x40000000
531 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
532 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
533 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
534 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
535 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
536 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
538 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
539 E1000_GCR_RXDSCW_NO_SNOOP | \
540 E1000_GCR_RXDSCR_NO_SNOOP | \
541 E1000_GCR_TXD_NO_SNOOP | \
542 E1000_GCR_TXDSCW_NO_SNOOP | \
543 E1000_GCR_TXDSCR_NO_SNOOP)
546 #define MII_CR_FULL_DUPLEX 0x0100
547 #define MII_CR_RESTART_AUTO_NEG 0x0200
548 #define MII_CR_POWER_DOWN 0x0800
549 #define MII_CR_AUTO_NEG_EN 0x1000
550 #define MII_CR_LOOPBACK 0x4000
551 #define MII_CR_RESET 0x8000
552 #define MII_CR_SPEED_1000 0x0040
553 #define MII_CR_SPEED_100 0x2000
554 #define MII_CR_SPEED_10 0x0000
557 #define MII_SR_LINK_STATUS 0x0004
558 #define MII_SR_AUTONEG_COMPLETE 0x0020
561 #define NWAY_AR_10T_HD_CAPS 0x0020
562 #define NWAY_AR_10T_FD_CAPS 0x0040
563 #define NWAY_AR_100TX_HD_CAPS 0x0080
564 #define NWAY_AR_100TX_FD_CAPS 0x0100
565 #define NWAY_AR_PAUSE 0x0400
566 #define NWAY_AR_ASM_DIR 0x0800
569 #define NWAY_LPAR_100TX_FD_CAPS 0x0100
570 #define NWAY_LPAR_PAUSE 0x0400
571 #define NWAY_LPAR_ASM_DIR 0x0800
574 #define NWAY_ER_LP_NWAY_CAPS 0x0001
577 #define CR_1000T_HD_CAPS 0x0100
578 #define CR_1000T_FD_CAPS 0x0200
580 #define CR_1000T_MS_VALUE 0x0800
582 #define CR_1000T_MS_ENABLE 0x1000
586 #define SR_1000T_REMOTE_RX_STATUS 0x1000
587 #define SR_1000T_LOCAL_RX_STATUS 0x2000
592 #define PHY_CONTROL 0x00
593 #define PHY_STATUS 0x01
596 #define PHY_AUTONEG_ADV 0x04
597 #define PHY_LP_ABILITY 0x05
598 #define PHY_AUTONEG_EXP 0x06
599 #define PHY_1000T_CTRL 0x09
600 #define PHY_1000T_STATUS 0x0A
601 #define PHY_EXT_STATUS 0x0F
603 #define PHY_CONTROL_LB 0x4000
606 #define E1000_EECD_SK 0x00000001
607 #define E1000_EECD_CS 0x00000002
608 #define E1000_EECD_DI 0x00000004
609 #define E1000_EECD_DO 0x00000008
610 #define E1000_EECD_REQ 0x00000040
611 #define E1000_EECD_GNT 0x00000080
612 #define E1000_EECD_PRES 0x00000100
613 #define E1000_EECD_SIZE 0x00000200
615 #define E1000_EECD_ADDR_BITS 0x00000400
616 #define E1000_NVM_GRANT_ATTEMPTS 1000
617 #define E1000_EECD_AUTO_RD 0x00000200
618 #define E1000_EECD_SIZE_EX_MASK 0x00007800
619 #define E1000_EECD_SIZE_EX_SHIFT 11
620 #define E1000_EECD_FLUPD 0x00080000
621 #define E1000_EECD_AUPDEN 0x00100000
622 #define E1000_EECD_SEC1VAL 0x00400000
623 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
625 #define E1000_NVM_RW_REG_DATA 16
626 #define E1000_NVM_RW_REG_DONE 2
627 #define E1000_NVM_RW_REG_START 1
628 #define E1000_NVM_RW_ADDR_SHIFT 2
629 #define E1000_NVM_POLL_WRITE 1
630 #define E1000_NVM_POLL_READ 0
631 #define E1000_FLASH_UPDATES 2000
634 #define NVM_COMPAT 0x0003
635 #define NVM_ID_LED_SETTINGS 0x0004
636 #define NVM_INIT_CONTROL2_REG 0x000F
637 #define NVM_INIT_CONTROL3_PORT_B 0x0014
638 #define NVM_INIT_3GIO_3 0x001A
639 #define NVM_INIT_CONTROL3_PORT_A 0x0024
640 #define NVM_CFG 0x0012
641 #define NVM_ALT_MAC_ADDR_PTR 0x0037
642 #define NVM_CHECKSUM_REG 0x003F
644 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000
646 #define E1000_NVM_CFG_DONE_PORT_0 0x40000
647 #define E1000_NVM_CFG_DONE_PORT_1 0x80000
650 #define NVM_WORD0F_PAUSE_MASK 0x3000
651 #define NVM_WORD0F_PAUSE 0x1000
652 #define NVM_WORD0F_ASM_DIR 0x2000
655 #define NVM_WORD1A_ASPM_MASK 0x000C
658 #define NVM_COMPAT_LOM 0x0800
661 #define E1000_PBANUM_LENGTH 11
664 #define NVM_SUM 0xBABA
667 #define NVM_PBA_OFFSET_0 8
668 #define NVM_PBA_OFFSET_1 9
669 #define NVM_PBA_PTR_GUARD 0xFAFA
670 #define NVM_WORD_SIZE_BASE_SHIFT 6
673 #define NVM_MAX_RETRY_SPI 5000
674 #define NVM_READ_OPCODE_SPI 0x03
675 #define NVM_WRITE_OPCODE_SPI 0x02
676 #define NVM_A8_OPCODE_SPI 0x08
677 #define NVM_WREN_OPCODE_SPI 0x06
678 #define NVM_RDSR_OPCODE_SPI 0x05
681 #define NVM_STATUS_RDY_SPI 0x01
684 #define ID_LED_RESERVED_0000 0x0000
685 #define ID_LED_RESERVED_FFFF 0xFFFF
686 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
687 (ID_LED_OFF1_OFF2 << 8) | \
688 (ID_LED_DEF1_DEF2 << 4) | \
690 #define ID_LED_DEF1_DEF2 0x1
691 #define ID_LED_DEF1_ON2 0x2
692 #define ID_LED_DEF1_OFF2 0x3
693 #define ID_LED_ON1_DEF2 0x4
694 #define ID_LED_ON1_ON2 0x5
695 #define ID_LED_ON1_OFF2 0x6
696 #define ID_LED_OFF1_DEF2 0x7
697 #define ID_LED_OFF1_ON2 0x8
698 #define ID_LED_OFF1_OFF2 0x9
700 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
701 #define IGP_ACTIVITY_LED_ENABLE 0x0300
702 #define IGP_LED3_MODE 0x07000000
705 #define PCI_HEADER_TYPE_REGISTER 0x0E
706 #define PCIE_LINK_STATUS 0x12
708 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
709 #define PCIE_LINK_WIDTH_MASK 0x3F0
710 #define PCIE_LINK_WIDTH_SHIFT 4
712 #define PHY_REVISION_MASK 0xFFFFFFF0
713 #define MAX_PHY_REG_ADDRESS 0x1F
714 #define MAX_PHY_MULTI_PAGE_REG 0xF
721 #define M88E1000_E_PHY_ID 0x01410C50
722 #define M88E1000_I_PHY_ID 0x01410C30
723 #define M88E1011_I_PHY_ID 0x01410C20
724 #define IGP01E1000_I_PHY_ID 0x02A80380
725 #define M88E1111_I_PHY_ID 0x01410CC0
726 #define GG82563_E_PHY_ID 0x01410CA0
727 #define IGP03E1000_E_PHY_ID 0x02A80390
728 #define IFE_E_PHY_ID 0x02A80330
729 #define IFE_PLUS_E_PHY_ID 0x02A80320
730 #define IFE_C_E_PHY_ID 0x02A80310
731 #define BME1000_E_PHY_ID 0x01410CB0
732 #define BME1000_E_PHY_ID_R2 0x01410CB1
733 #define I82577_E_PHY_ID 0x01540050
734 #define I82578_E_PHY_ID 0x004DD040
735 #define I82579_E_PHY_ID 0x01540090
736 #define I217_E_PHY_ID 0x015400A0
739 #define M88E1000_PHY_SPEC_CTRL 0x10
740 #define M88E1000_PHY_SPEC_STATUS 0x11
741 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14
743 #define M88E1000_PHY_PAGE_SELECT 0x1D
744 #define M88E1000_PHY_GEN_CONTROL 0x1E
747 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
748 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
750 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
752 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
754 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
759 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
762 #define M88E1000_PSSR_REV_POLARITY 0x0002
763 #define M88E1000_PSSR_DOWNSHIFT 0x0020
764 #define M88E1000_PSSR_MDIX 0x0040
766 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
767 #define M88E1000_PSSR_SPEED 0xC000
768 #define M88E1000_PSSR_1000MBS 0x8000
770 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
776 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
777 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
782 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
783 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
784 #define M88E1000_EPSCR_TX_CLK_25 0x0070
787 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
788 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
790 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
791 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
794 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800
797 #define PHY_PAGE_SHIFT 5
798 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
799 ((reg) & MAX_PHY_REG_ADDRESS))
806 #define GG82563_PAGE_SHIFT 5
807 #define GG82563_REG(page, reg) \
808 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
809 #define GG82563_MIN_ALT_REG 30
812 #define GG82563_PHY_SPEC_CTRL \
814 #define GG82563_PHY_PAGE_SELECT \
816 #define GG82563_PHY_SPEC_CTRL_2 \
818 #define GG82563_PHY_PAGE_SELECT_ALT \
821 #define GG82563_PHY_MAC_SPEC_CTRL \
824 #define GG82563_PHY_DSP_DISTANCE \
828 #define GG82563_PHY_KMRN_MODE_CTRL \
830 #define GG82563_PHY_PWR_MGMT_CTRL \
834 #define GG82563_PHY_INBAND_CTRL \
838 #define E1000_MDIC_REG_SHIFT 16
839 #define E1000_MDIC_PHY_SHIFT 21
840 #define E1000_MDIC_OP_WRITE 0x04000000
841 #define E1000_MDIC_OP_READ 0x08000000
842 #define E1000_MDIC_READY 0x10000000
843 #define E1000_MDIC_ERROR 0x40000000
846 #define E1000_GEN_POLL_TIMEOUT 640
849 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380
850 #define E1000_FWSM_WLOCK_MAC_SHIFT 7