Xenomai  3.0-rc7
igb.h
1 /*******************************************************************************
2 
3  Intel(R) Gigabit Ethernet Linux driver
4  Copyright(c) 2007 Intel Corporation.
5  RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
6 
7  This program is free software; you can redistribute it and/or modify it
8  under the terms and conditions of the GNU General Public License,
9  version 2, as published by the Free Software Foundation.
10 
11  This program is distributed in the hope it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc.,
18  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 
20  The full GNU General Public License is included in this distribution in
21  the file called "COPYING".
22 
23  Contact Information:
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 
30 /* Linux PRO/1000 Ethernet Driver main header file */
31 
32 #ifndef _IGB_H_
33 #define _IGB_H_
34 
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
37 #include <rtdev.h>
38 
39 struct igb_adapter;
40 
41 #ifdef CONFIG_IGB_LRO
42 #include <linux/inet_lro.h>
43 #define MAX_LRO_AGGR 32
44 #define MAX_LRO_DESCRIPTORS 8
45 #endif
46 
47 /* Interrupt defines */
48 #define IGB_MIN_DYN_ITR 3000
49 #define IGB_MAX_DYN_ITR 96000
50 
51 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
52 #define IGB_START_ITR 648
53 
54 #define IGB_DYN_ITR_PACKET_THRESHOLD 2
55 #define IGB_DYN_ITR_LENGTH_LOW 200
56 #define IGB_DYN_ITR_LENGTH_HIGH 1000
57 
58 /* TX/RX descriptor defines */
59 #define IGB_DEFAULT_TXD 256
60 #define IGB_MIN_TXD 80
61 #define IGB_MAX_TXD 4096
62 
63 #define IGB_DEFAULT_RXD 256
64 #define IGB_MIN_RXD 80
65 #define IGB_MAX_RXD 4096
66 
67 #define IGB_DEFAULT_ITR 3 /* dynamic */
68 #define IGB_MAX_ITR_USECS 10000
69 #define IGB_MIN_ITR_USECS 10
70 
71 /* Transmit and receive queues */
72 #define IGB_MAX_RX_QUEUES 4
73 #define IGB_MAX_TX_QUEUES 4
74 
75 /* RX descriptor control thresholds.
76  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
77  * descriptors available in its onboard memory.
78  * Setting this to 0 disables RX descriptor prefetch.
79  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
80  * available in host memory.
81  * If PTHRESH is 0, this should also be 0.
82  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
83  * descriptors until either it has this many to write back, or the
84  * ITR timer expires.
85  */
86 #define IGB_RX_PTHRESH 16
87 #define IGB_RX_HTHRESH 8
88 #define IGB_RX_WTHRESH 1
89 
90 /* this is the size past which hardware will drop packets when setting LPE=0 */
91 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
92 
93 /* Supported Rx Buffer Sizes */
94 #define IGB_RXBUFFER_128 128 /* Used for packet split */
95 #define IGB_RXBUFFER_256 256 /* Used for packet split */
96 #define IGB_RXBUFFER_512 512
97 #define IGB_RXBUFFER_1024 1024
98 #define IGB_RXBUFFER_2048 2048
99 #define IGB_RXBUFFER_4096 4096
100 #define IGB_RXBUFFER_8192 8192
101 #define IGB_RXBUFFER_16384 16384
102 
103 /* Packet Buffer allocations */
104 
105 
106 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
107 #define IGB_TX_QUEUE_WAKE 16
108 /* How many Rx Buffers do we bundle into one write to the hardware ? */
109 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
110 
111 #define AUTO_ALL_MODES 0
112 #define IGB_EEPROM_APME 0x0400
113 
114 #ifndef IGB_MASTER_SLAVE
115 /* Switch to override PHY master/slave setting */
116 #define IGB_MASTER_SLAVE e1000_ms_hw_default
117 #endif
118 
119 #define IGB_MNG_VLAN_NONE -1
120 
121 /* wrapper around a pointer to a socket buffer,
122  * so a DMA handle can be stored along with the buffer */
123 struct igb_buffer {
124  struct rtskb *skb;
125  dma_addr_t dma;
126  union {
127  /* TX */
128  struct {
129  unsigned long time_stamp;
130  u16 length;
131  u16 next_to_watch;
132  };
133  /* RX */
134  struct {
135  struct page *page;
136  u64 page_dma;
137  unsigned int page_offset;
138  };
139  };
140 };
141 
142 struct igb_queue_stats {
143  u64 packets;
144  u64 bytes;
145 };
146 
147 struct igb_ring {
148  struct igb_adapter *adapter; /* backlink */
149  void *desc; /* descriptor ring memory */
150  dma_addr_t dma; /* phys address of the ring */
151  unsigned int size; /* length of desc. ring in bytes */
152  unsigned int count; /* number of desc. in the ring */
153  u16 next_to_use;
154  u16 next_to_clean;
155  u16 head;
156  u16 tail;
157  struct igb_buffer *buffer_info; /* array of buffer info structs */
158 
159  u32 eims_value;
160  u32 itr_val;
161  u16 itr_register;
162  u16 cpu;
163 
164  u16 queue_index;
165  u16 reg_idx;
166  unsigned int total_bytes;
167  unsigned int total_packets;
168 
169  rtdm_lock_t lock;
170  rtdm_irq_t irq_handle;
171 
172  union {
173  /* TX */
174  struct {
175  struct igb_queue_stats tx_stats;
176  bool detect_tx_hung;
177  };
178  /* RX */
179  struct {
180  struct igb_queue_stats rx_stats;
181  struct napi_struct napi;
182  int set_itr;
183  struct igb_ring *buddy;
184 #ifdef CONFIG_IGB_LRO
185  struct net_lro_mgr lro_mgr;
186  bool lro_used;
187 #endif
188  };
189  };
190 
191  char name[IFNAMSIZ + 5];
192 };
193 
194 #define IGB_DESC_UNUSED(R) \
195  ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
196  (R)->next_to_clean - (R)->next_to_use - 1)
197 
198 #define E1000_RX_DESC_ADV(R, i) \
199  (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
200 #define E1000_TX_DESC_ADV(R, i) \
201  (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
202 #define E1000_TX_CTXTDESC_ADV(R, i) \
203  (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
204 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
205 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
206 #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
207 
208 /* board specific private data structure */
209 
210 struct igb_adapter {
211  struct timer_list watchdog_timer;
212  struct timer_list phy_info_timer;
213  struct vlan_group *vlgrp;
214  u16 mng_vlan_id;
215  u32 bd_number;
216  u32 rx_buffer_len;
217  u32 wol;
218  u32 en_mng_pt;
219  u16 link_speed;
220  u16 link_duplex;
221  unsigned int total_tx_bytes;
222  unsigned int total_tx_packets;
223  unsigned int total_rx_bytes;
224  unsigned int total_rx_packets;
225  /* Interrupt Throttle Rate */
226  u32 itr;
227  u32 itr_setting;
228  u16 tx_itr;
229  u16 rx_itr;
230 
231  struct work_struct reset_task;
232  struct work_struct watchdog_task;
233  bool fc_autoneg;
234  u8 tx_timeout_factor;
235  struct timer_list blink_timer;
236  unsigned long led_status;
237 
238  /* TX */
239  struct igb_ring *tx_ring; /* One per active queue */
240  unsigned int restart_queue;
241  unsigned long tx_queue_len;
242  u32 txd_cmd;
243  u32 gotc;
244  u64 gotc_old;
245  u64 tpt_old;
246  u64 colc_old;
247  u32 tx_timeout_count;
248 
249  /* RX */
250  struct igb_ring *rx_ring; /* One per active queue */
251  int num_tx_queues;
252  int num_rx_queues;
253 
254  u64 hw_csum_err;
255  u64 hw_csum_good;
256  u64 rx_hdr_split;
257  u32 alloc_rx_buff_failed;
258  bool rx_csum;
259  u32 gorc;
260  u64 gorc_old;
261  u16 rx_ps_hdr_size;
262  u32 max_frame_size;
263  u32 min_frame_size;
264 
265  /* OS defined structs */
266  struct rtnet_device *netdev;
267 
268  // struct napi_struct napi;
269  struct pci_dev *pdev;
270  struct net_device_stats net_stats;
271 
272  rtdm_irq_t irq_handle;
273  rtdm_nrtsig_t mod_timer_sig;
274 
275  /* structs defined in e1000_hw.h */
276  struct e1000_hw hw;
277  struct e1000_hw_stats stats;
278  struct e1000_phy_info phy_info;
279  struct e1000_phy_stats phy_stats;
280 
281  //#ifdef ETHTOOL_TEST
282  u32 test_icr;
283  struct igb_ring test_tx_ring;
284  struct igb_ring test_rx_ring;
285  //#endif
286 
287  int msg_enable;
288  struct msix_entry *msix_entries;
289  u32 eims_enable_mask;
290  u32 eims_other;
291 
292  /* to not mess up cache alignment, always add to the bottom */
293  unsigned long state;
294  unsigned int flags;
295  u32 eeprom_wol;
296 
297  /* for ioport free */
298  int bars;
299  int need_ioport;
300 
301  struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
302 #ifdef CONFIG_IGB_LRO
303  unsigned int lro_max_aggr;
304  unsigned int lro_aggregated;
305  unsigned int lro_flushed;
306  unsigned int lro_no_desc;
307 #endif
308  unsigned int tx_ring_count;
309  unsigned int rx_ring_count;
310 };
311 
312 #define IGB_FLAG_HAS_MSI (1 << 0)
313 #define IGB_FLAG_MSI_ENABLE (1 << 1)
314 #define IGB_FLAG_DCA_ENABLED (1 << 2)
315 #define IGB_FLAG_IN_NETPOLL (1 << 3)
316 #define IGB_FLAG_QUAD_PORT_A (1 << 4)
317 #define IGB_FLAG_NEED_CTX_IDX (1 << 5)
318 
319 enum e1000_state_t {
320  __IGB_TESTING,
321  __IGB_RESETTING,
322  __IGB_DOWN
323 };
324 
325 enum igb_boards {
326  board_82575,
327 };
328 
329 extern char igb_driver_name[];
330 extern char igb_driver_version[];
331 
332 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
333 extern int igb_up(struct igb_adapter *);
334 extern void igb_down(struct igb_adapter *);
335 extern void igb_reinit_locked(struct igb_adapter *);
336 extern void igb_reset(struct igb_adapter *);
337 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
338 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
339 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
340 extern void igb_free_tx_resources(struct igb_ring *);
341 extern void igb_free_rx_resources(struct igb_ring *);
342 extern void igb_update_stats(struct igb_adapter *);
343 extern void igb_set_ethtool_ops(struct net_device *);
344 
345 static inline s32 igb_reset_phy(struct e1000_hw *hw)
346 {
347  if (hw->phy.ops.reset_phy)
348  return hw->phy.ops.reset_phy(hw);
349 
350  return 0;
351 }
352 
353 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
354 {
355  if (hw->phy.ops.read_phy_reg)
356  return hw->phy.ops.read_phy_reg(hw, offset, data);
357 
358  return 0;
359 }
360 
361 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
362 {
363  if (hw->phy.ops.write_phy_reg)
364  return hw->phy.ops.write_phy_reg(hw, offset, data);
365 
366  return 0;
367 }
368 
369 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
370 {
371  if (hw->phy.ops.get_phy_info)
372  return hw->phy.ops.get_phy_info(hw);
373 
374  return 0;
375 }
376 
377 #endif /* _IGB_H_ */
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:528