15 #ifndef __RT_MPC52XX_FEC_H_
16 #define __RT_MPC52XX_FEC_H_
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/spinlock.h>
21 #include <linux/mii.h>
22 #include <linux/skbuff.h>
23 #include <asm/mpc5xxx.h>
24 #include <bestcomm_api.h>
27 #define CONFIG_XENO_DRIVERS_NET_USE_MDIO
28 #define CONFIG_XENO_DRIVERS_NET_FEC_GENERIC_PHY
29 #define CONFIG_XENO_DRIVERS_NET_FEC_LXT971
30 #undef CONFIG_XENO_DRIVERS_NET_FEC_DP83847
33 #define MPC5xxx_FEC_RECV_BUFFER_SIZE 1518
34 #define MPC5xxx_FEC_RECV_BUFFER_SIZE_BC 2048
35 #define MPC5xxx_FEC_TBD_NUM 256
36 #define MPC5xxx_FEC_RBD_NUM 256
43 volatile u32 reserved0[1];
44 volatile u32 r_des_active;
45 volatile u32 x_des_active;
46 volatile u32 r_des_active_cl;
47 volatile u32 x_des_active_cl;
48 volatile u32 ivent_set;
51 volatile u32 reserved1[6];
52 volatile u32 mii_data;
53 volatile u32 mii_speed;
54 volatile u32 mii_status;
56 volatile u32 reserved2[5];
57 volatile u32 mib_data;
58 volatile u32 mib_control;
60 volatile u32 reserved3[6];
61 volatile u32 r_activate;
68 volatile u32 r_da_low;
69 volatile u32 r_da_high;
71 volatile u32 reserved4[7];
72 volatile u32 x_activate;
76 volatile u32 x_status;
79 volatile u32 fdxfc_da1;
80 volatile u32 fdxfc_da2;
83 volatile u32 op_pause;
85 volatile u32 reserved5[4];
86 volatile u32 instr_reg;
87 volatile u32 context_reg;
88 volatile u32 test_cntrl;
100 volatile u32 reserved6[3];
101 volatile u32 fifo_id;
104 volatile u32 r_bound;
105 volatile u32 r_fstart;
106 volatile u32 r_count;
109 volatile u32 r_write;
110 volatile u32 x_count;
112 volatile u32 x_retry;
113 volatile u32 x_write;
116 volatile u32 reserved7[2];
117 volatile u32 fm_cntrl;
118 volatile u32 rfifo_data;
119 volatile u32 rfifo_status;
120 volatile u32 rfifo_cntrl;
121 volatile u32 rfifo_lrf_ptr;
122 volatile u32 rfifo_lwf_ptr;
123 volatile u32 rfifo_alarm;
124 volatile u32 rfifo_rdptr;
125 volatile u32 rfifo_wrptr;
126 volatile u32 tfifo_data;
127 volatile u32 tfifo_status;
128 volatile u32 tfifo_cntrl;
129 volatile u32 tfifo_lrf_ptr;
130 volatile u32 tfifo_lwf_ptr;
131 volatile u32 tfifo_alarm;
132 volatile u32 tfifo_rdptr;
133 volatile u32 tfifo_wrptr;
135 volatile u32 reset_cntrl;
136 volatile u32 xmit_fsm;
138 volatile u32 reserved8[3];
139 volatile u32 rdes_data0;
140 volatile u32 rdes_data1;
141 volatile u32 r_length;
142 volatile u32 x_length;
144 volatile u32 cdes_data;
146 volatile u32 dma_control;
147 volatile u32 des_cmnd;
150 volatile u32 rmon_t_drop;
151 volatile u32 rmon_t_packets;
152 volatile u32 rmon_t_bc_pkt;
153 volatile u32 rmon_t_mc_pkt;
154 volatile u32 rmon_t_crc_align;
155 volatile u32 rmon_t_undersize;
156 volatile u32 rmon_t_oversize;
157 volatile u32 rmon_t_frag;
158 volatile u32 rmon_t_jab;
159 volatile u32 rmon_t_col;
160 volatile u32 rmon_t_p64;
161 volatile u32 rmon_t_p65to127;
162 volatile u32 rmon_t_p128to255;
163 volatile u32 rmon_t_p256to511;
164 volatile u32 rmon_t_p512to1023;
165 volatile u32 rmon_t_p1024to2047;
166 volatile u32 rmon_t_p_gte2048;
167 volatile u32 rmon_t_octets;
168 volatile u32 ieee_t_drop;
169 volatile u32 ieee_t_frame_ok;
170 volatile u32 ieee_t_1col;
171 volatile u32 ieee_t_mcol;
172 volatile u32 ieee_t_def;
173 volatile u32 ieee_t_lcol;
174 volatile u32 ieee_t_excol;
175 volatile u32 ieee_t_macerr;
176 volatile u32 ieee_t_cserr;
177 volatile u32 ieee_t_sqe;
178 volatile u32 t_fdxfc;
179 volatile u32 ieee_t_octets_ok;
181 volatile u32 reserved9[2];
182 volatile u32 rmon_r_drop;
183 volatile u32 rmon_r_packets;
184 volatile u32 rmon_r_bc_pkt;
185 volatile u32 rmon_r_mc_pkt;
186 volatile u32 rmon_r_crc_align;
187 volatile u32 rmon_r_undersize;
188 volatile u32 rmon_r_oversize;
189 volatile u32 rmon_r_frag;
190 volatile u32 rmon_r_jab;
192 volatile u32 rmon_r_resvd_0;
194 volatile u32 rmon_r_p64;
195 volatile u32 rmon_r_p65to127;
196 volatile u32 rmon_r_p128to255;
197 volatile u32 rmon_r_p256to511;
198 volatile u32 rmon_r_p512to1023;
199 volatile u32 rmon_r_p1024to2047;
200 volatile u32 rmon_r_p_gte2048;
201 volatile u32 rmon_r_octets;
202 volatile u32 ieee_r_drop;
203 volatile u32 ieee_r_frame_ok;
204 volatile u32 ieee_r_crc;
205 volatile u32 ieee_r_align;
206 volatile u32 r_macerr;
207 volatile u32 r_fdxfc;
208 volatile u32 ieee_r_octets_ok;
210 volatile u32 reserved10[6];
212 volatile u32 reserved11[64];
215 #define MPC5xxx_FEC_MIB_DISABLE 0x80000000
217 #define MPC5xxx_FEC_IEVENT_HBERR 0x80000000
218 #define MPC5xxx_FEC_IEVENT_BABR 0x40000000
219 #define MPC5xxx_FEC_IEVENT_BABT 0x20000000
220 #define MPC5xxx_FEC_IEVENT_GRA 0x10000000
221 #define MPC5xxx_FEC_IEVENT_TFINT 0x08000000
222 #define MPC5xxx_FEC_IEVENT_MII 0x00800000
223 #define MPC5xxx_FEC_IEVENT_LATE_COL 0x00200000
224 #define MPC5xxx_FEC_IEVENT_COL_RETRY_LIM 0x00100000
225 #define MPC5xxx_FEC_IEVENT_XFIFO_UN 0x00080000
226 #define MPC5xxx_FEC_IEVENT_XFIFO_ERROR 0x00040000
227 #define MPC5xxx_FEC_IEVENT_RFIFO_ERROR 0x00020000
229 #define MPC5xxx_FEC_IMASK_HBERR 0x80000000
230 #define MPC5xxx_FEC_IMASK_BABR 0x40000000
231 #define MPC5xxx_FEC_IMASK_BABT 0x20000000
232 #define MPC5xxx_FEC_IMASK_GRA 0x10000000
233 #define MPC5xxx_FEC_IMASK_MII 0x00800000
234 #define MPC5xxx_FEC_IMASK_LATE_COL 0x00200000
235 #define MPC5xxx_FEC_IMASK_COL_RETRY_LIM 0x00100000
236 #define MPC5xxx_FEC_IMASK_XFIFO_UN 0x00080000
237 #define MPC5xxx_FEC_IMASK_XFIFO_ERROR 0x00040000
238 #define MPC5xxx_FEC_IMASK_RFIFO_ERROR 0x00020000
240 #define MPC5xxx_FEC_RCNTRL_MAX_FL_SHIFT 16
241 #define MPC5xxx_FEC_RCNTRL_LOOP 0x01
242 #define MPC5xxx_FEC_RCNTRL_DRT 0x02
243 #define MPC5xxx_FEC_RCNTRL_MII_MODE 0x04
244 #define MPC5xxx_FEC_RCNTRL_PROM 0x08
245 #define MPC5xxx_FEC_RCNTRL_BC_REJ 0x10
246 #define MPC5xxx_FEC_RCNTRL_FCE 0x20
248 #define MPC5xxx_FEC_TCNTRL_GTS 0x00000001
249 #define MPC5xxx_FEC_TCNTRL_HBC 0x00000002
250 #define MPC5xxx_FEC_TCNTRL_FDEN 0x00000004
251 #define MPC5xxx_FEC_TCNTRL_TFC_PAUSE 0x00000008
252 #define MPC5xxx_FEC_TCNTRL_RFC_PAUSE 0x00000010
254 #define MPC5xxx_FEC_ECNTRL_RESET 0x00000001
255 #define MPC5xxx_FEC_ECNTRL_ETHER_EN 0x00000002
257 #define MPC5xxx_FEC_RESET_DELAY 50
261 struct mpc5xxx_fec_bd {
267 struct mpc5xxx_rbuf {
268 u8 data[MPC5xxx_FEC_RECV_BUFFER_SIZE_BC];
272 volatile struct mpc5xxx_fec_bd *bd_base;
273 struct rtskb **skb_base;
279 #ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
280 #define MII_ADVERTISE_HALF (ADVERTISE_100HALF | ADVERTISE_10HALF | \
283 #define MII_ADVERTISE_ALL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
286 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_ALL
288 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_HALF
293 void (*funct)(uint mii_reg,
struct rtnet_device *dev, uint data);
300 const phy_cmd_t *config;
301 const phy_cmd_t *startup;
302 const phy_cmd_t *ack_int;
303 const phy_cmd_t *shutdown;
307 struct mpc5xxx_fec_priv {
314 rtdm_irq_t irq_handle;
315 rtdm_irq_t r_irq_handle;
316 rtdm_irq_t t_irq_handle;
317 u32 last_transmit_time;
318 u32 last_receive_time;
319 struct mpc5xxx_fec *fec;
320 struct mpc5xxx_sram_fec *sram;
321 struct mpc5xxx_gpio *gpio;
322 struct mpc5xxx_sdma *sdma;
323 struct fec_queue r_queue;
324 struct rtskb *rskb[MPC5xxx_FEC_RBD_NUM];
325 struct fec_queue t_queue;
326 struct rtskb *tskb[MPC5xxx_FEC_TBD_NUM];
328 unsigned long open_time;
329 struct net_device_stats stats;
330 #ifdef CONFIG_XENO_DRIVERS_NET_USE_MDIO
336 struct tq_struct phy_task;
337 volatile uint sequence_done;
341 struct tq_struct link_up_task;
345 struct timer_list phy_timer_list;
350 struct mpc5xxx_sram_fec {
351 volatile struct mpc5xxx_fec_bd tbd[MPC5xxx_FEC_TBD_NUM];
352 volatile struct mpc5xxx_fec_bd rbd[MPC5xxx_FEC_RBD_NUM];
355 #define MPC5xxx_FEC_RBD_READY 0x40000000
356 #define MPC5xxx_FEC_RBD_RFD 0x08000000
358 #define MPC5xxx_FEC_RBD_INIT MPC5xxx_FEC_RBD_READY
360 #define MPC5xxx_FEC_TBD_READY 0x40000000
361 #define MPC5xxx_FEC_TBD_TFD 0x08000000
362 #define MPC5xxx_FEC_TBD_INT 0x04000000
364 #define MPC5xxx_FEC_TBD_INIT (MPC5xxx_FEC_TBD_INT | MPC5xxx_FEC_TBD_TFD | \
365 MPC5xxx_FEC_TBD_READY)
370 #define MPC5xxx_FEC_MII_DATA_ST 0x40000000
371 #define MPC5xxx_FEC_MII_DATA_OP_RD 0x20000000
372 #define MPC5xxx_FEC_MII_DATA_OP_WR 0x10000000
373 #define MPC5xxx_FEC_MII_DATA_PA_MSK 0x0f800000
374 #define MPC5xxx_FEC_MII_DATA_RA_MSK 0x007c0000
375 #define MPC5xxx_FEC_MII_DATA_TA 0x00020000
376 #define MPC5xxx_FEC_MII_DATA_DATAMSK 0x00000fff
378 #define MPC5xxx_FEC_MII_DATA_RA_SHIFT 0x12
379 #define MPC5xxx_FEC_MII_DATA_PA_SHIFT 0x17
381 #define MPC5xxx_FEC_MII_SPEED (5 * 2)
383 const char mpc5xxx_fec_name[] =
"eth0";
386 unsigned int byteReceived;
387 unsigned int byteSent;
388 unsigned int framesReceived;
389 unsigned int framesSent;
390 unsigned int totalByteReceived;
391 unsigned int totalFramesReceived;
392 unsigned int broadcastFramesReceived;
393 unsigned int multicastFramesReceived;
394 unsigned int cRCError;
395 unsigned int oversizeFrames;
396 unsigned int fragments;
398 unsigned int collision;
399 unsigned int lateCollision;
400 unsigned int frames64;
401 unsigned int frames65_127;
402 unsigned int frames128_255;
403 unsigned int frames256_511;
404 unsigned int frames512_1023;
405 unsigned int frames1024_MaxSize;
406 unsigned int macRxError;
407 unsigned int droppedFrames;
408 unsigned int outMulticastFrames;
409 unsigned int outBroadcastFrames;
410 unsigned int undersizeFrames;
413 #define MPC5xxx_FEC_WATCHDOG_TIMEOUT ((400*HZ)/1000)
416 #define MPC5xxx_FEC_FRAME_LAST 0x08000000
417 #define MPC5xxx_FEC_FRAME_M 0x01000000
418 #define MPC5xxx_FEC_FRAME_BC 0x00800000
419 #define MPC5xxx_FEC_FRAME_MC 0x00400000
420 #define MPC5xxx_FEC_FRAME_LG 0x00200000
421 #define MPC5xxx_FEC_FRAME_NO 0x00100000
422 #define MPC5xxx_FEC_FRAME_CR 0x00040000
423 #define MPC5xxx_FEC_FRAME_OV 0x00020000
424 #define MPC5xxx_FEC_FRAME_TR 0x00010000
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:528