29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
33 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
34 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
38 #define E1000_WUC_APME 0x00000001
39 #define E1000_WUC_PME_EN 0x00000002
40 #define E1000_WUC_PME_STATUS 0x00000004
41 #define E1000_WUC_APMPME 0x00000008
42 #define E1000_WUC_LSCWE 0x00000010
43 #define E1000_WUC_LSCWO 0x00000020
44 #define E1000_WUC_SPM 0x80000000
45 #define E1000_WUC_PHY_WAKE 0x00000100
48 #define E1000_WUFC_LNKC 0x00000001
49 #define E1000_WUFC_MAG 0x00000002
50 #define E1000_WUFC_EX 0x00000004
51 #define E1000_WUFC_MC 0x00000008
52 #define E1000_WUFC_BC 0x00000010
53 #define E1000_WUFC_ARP 0x00000020
54 #define E1000_WUFC_IPV4 0x00000040
55 #define E1000_WUFC_IPV6 0x00000080
56 #define E1000_WUFC_IGNORE_TCO 0x00008000
57 #define E1000_WUFC_FLX0 0x00010000
58 #define E1000_WUFC_FLX1 0x00020000
59 #define E1000_WUFC_FLX2 0x00040000
60 #define E1000_WUFC_FLX3 0x00080000
61 #define E1000_WUFC_ALL_FILTERS 0x000F00FF
62 #define E1000_WUFC_FLX_OFFSET 16
63 #define E1000_WUFC_FLX_FILTERS 0x000F0000
66 #define E1000_WUS_LNKC E1000_WUFC_LNKC
67 #define E1000_WUS_MAG E1000_WUFC_MAG
68 #define E1000_WUS_EX E1000_WUFC_EX
69 #define E1000_WUS_MC E1000_WUFC_MC
70 #define E1000_WUS_BC E1000_WUFC_BC
71 #define E1000_WUS_ARP E1000_WUFC_ARP
72 #define E1000_WUS_IPV4 E1000_WUFC_IPV4
73 #define E1000_WUS_IPV6 E1000_WUFC_IPV6
74 #define E1000_WUS_FLX0 E1000_WUFC_FLX0
75 #define E1000_WUS_FLX1 E1000_WUFC_FLX1
76 #define E1000_WUS_FLX2 E1000_WUFC_FLX2
77 #define E1000_WUS_FLX3 E1000_WUFC_FLX3
78 #define E1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS
81 #define E1000_WUPL_LENGTH_MASK 0x0FFF
84 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
87 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
89 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
90 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
91 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
94 #define E1000_CTRL_EXT_GPI0_EN 0x00000001
95 #define E1000_CTRL_EXT_GPI1_EN 0x00000002
96 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
97 #define E1000_CTRL_EXT_GPI2_EN 0x00000004
98 #define E1000_CTRL_EXT_GPI3_EN 0x00000008
100 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010
101 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020
102 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
103 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040
104 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080
106 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100
107 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200
108 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400
109 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800
110 #define E1000_CTRL_EXT_ASDCHK 0x00001000
111 #define E1000_CTRL_EXT_EE_RST 0x00002000
112 #define E1000_CTRL_EXT_IPS 0x00004000
113 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000
114 #define E1000_CTRL_EXT_RO_DIS 0x00020000
115 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
116 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
117 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
118 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
119 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
120 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000
121 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
122 #define E1000_CTRL_EXT_EIAME 0x01000000
123 #define E1000_CTRL_EXT_IRCA 0x00000001
124 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
125 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
126 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
127 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
128 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
129 #define E1000_CTRL_EXT_CANC 0x04000000
130 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
132 #define E1000_CTRL_EXT_IAME 0x08000000
133 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000
134 #define E1000_CRTL_EXT_PB_PAREN 0x01000000
135 #define E1000_CTRL_EXT_DF_PAREN 0x02000000
136 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
137 #define E1000_CTRL_EXT_PBA_CLR 0x80000000
138 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
139 #define E1000_I2CCMD_REG_ADDR 0x00FF0000
140 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
141 #define E1000_I2CCMD_PHY_ADDR 0x07000000
142 #define E1000_I2CCMD_OPCODE_READ 0x08000000
143 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
144 #define E1000_I2CCMD_RESET 0x10000000
145 #define E1000_I2CCMD_READY 0x20000000
146 #define E1000_I2CCMD_INTERRUPT_ENA 0x40000000
147 #define E1000_I2CCMD_ERROR 0x80000000
148 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
149 #define E1000_I2CCMD_PHY_TIMEOUT 200
152 #define E1000_RXD_STAT_DD 0x01
153 #define E1000_RXD_STAT_EOP 0x02
154 #define E1000_RXD_STAT_IXSM 0x04
155 #define E1000_RXD_STAT_VP 0x08
156 #define E1000_RXD_STAT_UDPCS 0x10
157 #define E1000_RXD_STAT_TCPCS 0x20
158 #define E1000_RXD_STAT_IPCS 0x40
159 #define E1000_RXD_STAT_PIF 0x80
160 #define E1000_RXD_STAT_CRCV 0x100
161 #define E1000_RXD_STAT_IPIDV 0x200
162 #define E1000_RXD_STAT_UDPV 0x400
163 #define E1000_RXD_STAT_DYNINT 0x800
164 #define E1000_RXD_STAT_ACK 0x8000
165 #define E1000_RXD_ERR_CE 0x01
166 #define E1000_RXD_ERR_SE 0x02
167 #define E1000_RXD_ERR_SEQ 0x04
168 #define E1000_RXD_ERR_CXE 0x10
169 #define E1000_RXD_ERR_TCPE 0x20
170 #define E1000_RXD_ERR_IPE 0x40
171 #define E1000_RXD_ERR_RXE 0x80
172 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF
173 #define E1000_RXD_SPC_PRI_MASK 0xE000
174 #define E1000_RXD_SPC_PRI_SHIFT 13
175 #define E1000_RXD_SPC_CFI_MASK 0x1000
176 #define E1000_RXD_SPC_CFI_SHIFT 12
178 #define E1000_RXDEXT_STATERR_CE 0x01000000
179 #define E1000_RXDEXT_STATERR_SE 0x02000000
180 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
181 #define E1000_RXDEXT_STATERR_CXE 0x10000000
182 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
183 #define E1000_RXDEXT_STATERR_IPE 0x40000000
184 #define E1000_RXDEXT_STATERR_RXE 0x80000000
187 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
190 E1000_RXD_ERR_SEQ | \
191 E1000_RXD_ERR_CXE | \
195 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
196 E1000_RXDEXT_STATERR_CE | \
197 E1000_RXDEXT_STATERR_SE | \
198 E1000_RXDEXT_STATERR_SEQ | \
199 E1000_RXDEXT_STATERR_CXE | \
200 E1000_RXDEXT_STATERR_RXE)
202 #define E1000_MRQC_ENABLE_MASK 0x00000007
203 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
204 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
205 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
206 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
207 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
208 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
209 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
210 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
211 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
213 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
214 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
217 #define E1000_MANC_SMBUS_EN 0x00000001
218 #define E1000_MANC_ASF_EN 0x00000002
219 #define E1000_MANC_R_ON_FORCE 0x00000004
220 #define E1000_MANC_RMCP_EN 0x00000100
221 #define E1000_MANC_0298_EN 0x00000200
222 #define E1000_MANC_IPV4_EN 0x00000400
223 #define E1000_MANC_IPV6_EN 0x00000800
224 #define E1000_MANC_SNAP_EN 0x00001000
225 #define E1000_MANC_ARP_EN 0x00002000
227 #define E1000_MANC_NEIGHBOR_EN 0x00004000
228 #define E1000_MANC_ARP_RES_EN 0x00008000
229 #define E1000_MANC_TCO_RESET 0x00010000
230 #define E1000_MANC_RCV_TCO_EN 0x00020000
231 #define E1000_MANC_REPORT_STATUS 0x00040000
232 #define E1000_MANC_RCV_ALL 0x00080000
233 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
235 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
237 #define E1000_MANC_EN_MNG2HOST 0x00200000
239 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000
240 #define E1000_MANC_EN_XSUM_FILTER 0x00800000
241 #define E1000_MANC_BR_EN 0x01000000
242 #define E1000_MANC_SMB_REQ 0x01000000
243 #define E1000_MANC_SMB_GNT 0x02000000
244 #define E1000_MANC_SMB_CLK_IN 0x04000000
245 #define E1000_MANC_SMB_DATA_IN 0x08000000
246 #define E1000_MANC_SMB_DATA_OUT 0x10000000
247 #define E1000_MANC_SMB_CLK_OUT 0x20000000
249 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28
250 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29
253 #define E1000_RCTL_RST 0x00000001
254 #define E1000_RCTL_EN 0x00000002
255 #define E1000_RCTL_SBP 0x00000004
256 #define E1000_RCTL_UPE 0x00000008
257 #define E1000_RCTL_MPE 0x00000010
258 #define E1000_RCTL_LPE 0x00000020
259 #define E1000_RCTL_LBM_NO 0x00000000
260 #define E1000_RCTL_LBM_MAC 0x00000040
261 #define E1000_RCTL_LBM_SLP 0x00000080
262 #define E1000_RCTL_LBM_TCVR 0x000000C0
263 #define E1000_RCTL_DTYP_MASK 0x00000C00
264 #define E1000_RCTL_DTYP_PS 0x00000400
265 #define E1000_RCTL_RDMTS_HALF 0x00000000
266 #define E1000_RCTL_RDMTS_QUAT 0x00000100
267 #define E1000_RCTL_RDMTS_EIGTH 0x00000200
268 #define E1000_RCTL_MO_SHIFT 12
269 #define E1000_RCTL_MO_0 0x00000000
270 #define E1000_RCTL_MO_1 0x00001000
271 #define E1000_RCTL_MO_2 0x00002000
272 #define E1000_RCTL_MO_3 0x00003000
273 #define E1000_RCTL_MDR 0x00004000
274 #define E1000_RCTL_BAM 0x00008000
276 #define E1000_RCTL_SZ_2048 0x00000000
277 #define E1000_RCTL_SZ_1024 0x00010000
278 #define E1000_RCTL_SZ_512 0x00020000
279 #define E1000_RCTL_SZ_256 0x00030000
281 #define E1000_RCTL_SZ_16384 0x00010000
282 #define E1000_RCTL_SZ_8192 0x00020000
283 #define E1000_RCTL_SZ_4096 0x00030000
284 #define E1000_RCTL_VFE 0x00040000
285 #define E1000_RCTL_CFIEN 0x00080000
286 #define E1000_RCTL_CFI 0x00100000
287 #define E1000_RCTL_DPF 0x00400000
288 #define E1000_RCTL_PMCF 0x00800000
289 #define E1000_RCTL_BSEX 0x02000000
290 #define E1000_RCTL_SECRC 0x04000000
291 #define E1000_RCTL_FLXBUF_MASK 0x78000000
292 #define E1000_RCTL_FLXBUF_SHIFT 27
311 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
312 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
313 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
314 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
316 #define E1000_PSRCTL_BSIZE0_SHIFT 7
317 #define E1000_PSRCTL_BSIZE1_SHIFT 2
318 #define E1000_PSRCTL_BSIZE2_SHIFT 6
319 #define E1000_PSRCTL_BSIZE3_SHIFT 14
322 #define E1000_SWFW_EEP_SM 0x1
323 #define E1000_SWFW_PHY0_SM 0x2
324 #define E1000_SWFW_PHY1_SM 0x4
325 #define E1000_SWFW_CSR_SM 0x8
328 #define E1000_FACTPS_LFS 0x40000000
330 #define E1000_CTRL_FD 0x00000001
331 #define E1000_CTRL_BEM 0x00000002
332 #define E1000_CTRL_PRIOR 0x00000004
333 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
334 #define E1000_CTRL_LRST 0x00000008
335 #define E1000_CTRL_TME 0x00000010
336 #define E1000_CTRL_SLE 0x00000020
337 #define E1000_CTRL_ASDE 0x00000020
338 #define E1000_CTRL_SLU 0x00000040
339 #define E1000_CTRL_ILOS 0x00000080
340 #define E1000_CTRL_SPD_SEL 0x00000300
341 #define E1000_CTRL_SPD_10 0x00000000
342 #define E1000_CTRL_SPD_100 0x00000100
343 #define E1000_CTRL_SPD_1000 0x00000200
344 #define E1000_CTRL_BEM32 0x00000400
345 #define E1000_CTRL_FRCSPD 0x00000800
346 #define E1000_CTRL_FRCDPX 0x00001000
347 #define E1000_CTRL_D_UD_EN 0x00002000
348 #define E1000_CTRL_D_UD_POLARITY 0x00004000
349 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000
350 #define E1000_CTRL_EXT_LINK_EN 0x00010000
351 #define E1000_CTRL_SWDPIN0 0x00040000
352 #define E1000_CTRL_SWDPIN1 0x00080000
353 #define E1000_CTRL_SWDPIN2 0x00100000
354 #define E1000_CTRL_SWDPIN3 0x00200000
355 #define E1000_CTRL_SWDPIO0 0x00400000
356 #define E1000_CTRL_SWDPIO1 0x00800000
357 #define E1000_CTRL_SWDPIO2 0x01000000
358 #define E1000_CTRL_SWDPIO3 0x02000000
359 #define E1000_CTRL_RST 0x04000000
360 #define E1000_CTRL_RFCE 0x08000000
361 #define E1000_CTRL_TFCE 0x10000000
362 #define E1000_CTRL_RTE 0x20000000
363 #define E1000_CTRL_VME 0x40000000
364 #define E1000_CTRL_PHY_RST 0x80000000
365 #define E1000_CTRL_SW2FW_INT 0x02000000
366 #define E1000_CTRL_I2C_ENA 0x02000000
371 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
372 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
373 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
374 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
375 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
376 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
377 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
378 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
380 #define E1000_CONNSW_ENRGSRC 0x4
381 #define E1000_PCS_LCTL_FLV_LINK_UP 1
382 #define E1000_PCS_LCTL_FSV_10 0
383 #define E1000_PCS_LCTL_FSV_100 2
384 #define E1000_PCS_LCTL_FSV_1000 4
385 #define E1000_PCS_LCTL_FDV_FULL 8
386 #define E1000_PCS_LCTL_FSD 0x10
387 #define E1000_PCS_LCTL_FORCE_LINK 0x20
388 #define E1000_PCS_LCTL_LOW_LINK_LATCH 0x40
389 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
390 #define E1000_PCS_LCTL_AN_RESTART 0x20000
391 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
392 #define E1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000
393 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000
394 #define E1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000
395 #define E1000_PCS_LCTL_LINK_OK_FIX 0x2000000
396 #define E1000_PCS_LCTL_CRS_ON_NI 0x4000000
397 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
399 #define E1000_PCS_LSTS_LINK_OK 1
400 #define E1000_PCS_LSTS_SPEED_10 0
401 #define E1000_PCS_LSTS_SPEED_100 2
402 #define E1000_PCS_LSTS_SPEED_1000 4
403 #define E1000_PCS_LSTS_DUPLEX_FULL 8
404 #define E1000_PCS_LSTS_SYNK_OK 0x10
405 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
406 #define E1000_PCS_LSTS_AN_PAGE_RX 0x20000
407 #define E1000_PCS_LSTS_AN_TIMED_OUT 0x40000
408 #define E1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000
409 #define E1000_PCS_LSTS_AN_ERROR_RWS 0x100000
412 #define E1000_STATUS_FD 0x00000001
413 #define E1000_STATUS_LU 0x00000002
414 #define E1000_STATUS_FUNC_MASK 0x0000000C
415 #define E1000_STATUS_FUNC_SHIFT 2
416 #define E1000_STATUS_FUNC_0 0x00000000
417 #define E1000_STATUS_FUNC_1 0x00000004
418 #define E1000_STATUS_TXOFF 0x00000010
419 #define E1000_STATUS_TBIMODE 0x00000020
420 #define E1000_STATUS_SPEED_MASK 0x000000C0
421 #define E1000_STATUS_SPEED_10 0x00000000
422 #define E1000_STATUS_SPEED_100 0x00000040
423 #define E1000_STATUS_SPEED_1000 0x00000080
424 #define E1000_STATUS_LAN_INIT_DONE 0x00000200
425 #define E1000_STATUS_ASDV 0x00000300
426 #define E1000_STATUS_DOCK_CI 0x00000800
427 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
428 #define E1000_STATUS_MTXCKOK 0x00000400
429 #define E1000_STATUS_PCI66 0x00000800
430 #define E1000_STATUS_BUS64 0x00001000
431 #define E1000_STATUS_PCIX_MODE 0x00002000
432 #define E1000_STATUS_PCIX_SPEED 0x0000C000
433 #define E1000_STATUS_BMC_SKU_0 0x00100000
434 #define E1000_STATUS_BMC_SKU_1 0x00200000
435 #define E1000_STATUS_BMC_SKU_2 0x00400000
436 #define E1000_STATUS_BMC_CRYPTO 0x00800000
437 #define E1000_STATUS_BMC_LITE 0x01000000
438 #define E1000_STATUS_RGMII_ENABLE 0x02000000
439 #define E1000_STATUS_FUSE_8 0x04000000
440 #define E1000_STATUS_FUSE_9 0x08000000
441 #define E1000_STATUS_SERDES0_DIS 0x10000000
442 #define E1000_STATUS_SERDES1_DIS 0x20000000
445 #define E1000_STATUS_PCIX_SPEED_66 0x00000000
446 #define E1000_STATUS_PCIX_SPEED_100 0x00004000
447 #define E1000_STATUS_PCIX_SPEED_133 0x00008000
450 #define SPEED_100 100
451 #define SPEED_1000 1000
452 #define HALF_DUPLEX 1
453 #define FULL_DUPLEX 2
455 #define PHY_FORCE_TIME 20
457 #define ADVERTISE_10_HALF 0x0001
458 #define ADVERTISE_10_FULL 0x0002
459 #define ADVERTISE_100_HALF 0x0004
460 #define ADVERTISE_100_FULL 0x0008
461 #define ADVERTISE_1000_HALF 0x0010
462 #define ADVERTISE_1000_FULL 0x0020
465 #define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
466 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
468 #define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
469 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
470 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
471 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
472 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
474 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
476 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
479 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
480 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
481 #define E1000_LEDCTL_LED0_BLINK_RATE 0x00000020
482 #define E1000_LEDCTL_LED0_IVRT 0x00000040
483 #define E1000_LEDCTL_LED0_BLINK 0x00000080
484 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
485 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
486 #define E1000_LEDCTL_LED1_BLINK_RATE 0x00002000
487 #define E1000_LEDCTL_LED1_IVRT 0x00004000
488 #define E1000_LEDCTL_LED1_BLINK 0x00008000
489 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
490 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
491 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
492 #define E1000_LEDCTL_LED2_IVRT 0x00400000
493 #define E1000_LEDCTL_LED2_BLINK 0x00800000
494 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
495 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
496 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
497 #define E1000_LEDCTL_LED3_IVRT 0x40000000
498 #define E1000_LEDCTL_LED3_BLINK 0x80000000
500 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
501 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
502 #define E1000_LEDCTL_MODE_LINK_UP 0x2
503 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
504 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
505 #define E1000_LEDCTL_MODE_LINK_10 0x5
506 #define E1000_LEDCTL_MODE_LINK_100 0x6
507 #define E1000_LEDCTL_MODE_LINK_1000 0x7
508 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
509 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
510 #define E1000_LEDCTL_MODE_COLLISION 0xA
511 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
512 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
513 #define E1000_LEDCTL_MODE_PAUSED 0xD
514 #define E1000_LEDCTL_MODE_LED_ON 0xE
515 #define E1000_LEDCTL_MODE_LED_OFF 0xF
518 #define E1000_TXD_DTYP_D 0x00100000
519 #define E1000_TXD_DTYP_C 0x00000000
520 #define E1000_TXD_POPTS_SHIFT 8
521 #define E1000_TXD_POPTS_IXSM 0x01
522 #define E1000_TXD_POPTS_TXSM 0x02
523 #define E1000_TXD_CMD_EOP 0x01000000
524 #define E1000_TXD_CMD_IFCS 0x02000000
525 #define E1000_TXD_CMD_IC 0x04000000
526 #define E1000_TXD_CMD_RS 0x08000000
527 #define E1000_TXD_CMD_RPS 0x10000000
528 #define E1000_TXD_CMD_DEXT 0x20000000
529 #define E1000_TXD_CMD_VLE 0x40000000
530 #define E1000_TXD_CMD_IDE 0x80000000
531 #define E1000_TXD_STAT_DD 0x00000001
532 #define E1000_TXD_STAT_EC 0x00000002
533 #define E1000_TXD_STAT_LC 0x00000004
534 #define E1000_TXD_STAT_TU 0x00000008
535 #define E1000_TXD_CMD_TCP 0x01000000
536 #define E1000_TXD_CMD_IP 0x02000000
537 #define E1000_TXD_CMD_TSE 0x04000000
538 #define E1000_TXD_STAT_TC 0x00000004
542 #define E1000_TCTL_RST 0x00000001
543 #define E1000_TCTL_EN 0x00000002
544 #define E1000_TCTL_BCE 0x00000004
545 #define E1000_TCTL_PSP 0x00000008
546 #define E1000_TCTL_CT 0x00000ff0
547 #define E1000_TCTL_COLD 0x003ff000
548 #define E1000_TCTL_SWXOFF 0x00400000
549 #define E1000_TCTL_PBE 0x00800000
550 #define E1000_TCTL_RTLC 0x01000000
551 #define E1000_TCTL_NRTU 0x02000000
552 #define E1000_TCTL_MULR 0x10000000
555 #define E1000_TARC0_ENABLE 0x00000400
558 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
561 #define E1000_RXCSUM_PCSS_MASK 0x000000FF
562 #define E1000_RXCSUM_IPOFL 0x00000100
563 #define E1000_RXCSUM_TUOFL 0x00000200
564 #define E1000_RXCSUM_IPV6OFL 0x00000400
565 #define E1000_RXCSUM_CRCOFL 0x00000800
566 #define E1000_RXCSUM_IPPCSE 0x00001000
567 #define E1000_RXCSUM_PCSD 0x00002000
570 #define E1000_RFCTL_ISCSI_DIS 0x00000001
571 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
572 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
573 #define E1000_RFCTL_NFSW_DIS 0x00000040
574 #define E1000_RFCTL_NFSR_DIS 0x00000080
575 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
576 #define E1000_RFCTL_NFS_VER_SHIFT 8
577 #define E1000_RFCTL_IPV6_DIS 0x00000400
578 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
579 #define E1000_RFCTL_ACK_DIS 0x00001000
580 #define E1000_RFCTL_ACKD_DIS 0x00002000
581 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
582 #define E1000_RFCTL_EXTEN 0x00008000
583 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
584 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
587 #define E1000_COLLISION_THRESHOLD 15
588 #define E1000_CT_SHIFT 4
589 #define E1000_COLLISION_DISTANCE 63
590 #define E1000_COLD_SHIFT 12
593 #define DEFAULT_82542_TIPG_IPGT 10
594 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
595 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
597 #define E1000_TIPG_IPGT_MASK 0x000003FF
598 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
599 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
601 #define DEFAULT_82542_TIPG_IPGR1 2
602 #define DEFAULT_82543_TIPG_IPGR1 8
603 #define E1000_TIPG_IPGR1_SHIFT 10
605 #define DEFAULT_82542_TIPG_IPGR2 10
606 #define DEFAULT_82543_TIPG_IPGR2 6
607 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
608 #define E1000_TIPG_IPGR2_SHIFT 20
611 #define ETHERNET_IEEE_VLAN_TYPE 0x8100
613 #define ETHERNET_FCS_SIZE 4
614 #define MAX_JUMBO_FRAME_SIZE 0x3F00
617 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
618 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
619 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
620 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
621 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16
622 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
623 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16
625 #define E1000_PHY_CTRL_SPD_EN 0x00000001
626 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
627 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
628 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
629 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
631 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
634 #define E1000_PBA_8K 0x0008
635 #define E1000_PBA_12K 0x000C
636 #define E1000_PBA_16K 0x0010
637 #define E1000_PBA_20K 0x0014
638 #define E1000_PBA_22K 0x0016
639 #define E1000_PBA_24K 0x0018
640 #define E1000_PBA_30K 0x001E
641 #define E1000_PBA_32K 0x0020
642 #define E1000_PBA_34K 0x0022
643 #define E1000_PBA_38K 0x0026
644 #define E1000_PBA_40K 0x0028
645 #define E1000_PBA_48K 0x0030
646 #define E1000_PBA_64K 0x0040
648 #define E1000_PBS_16K E1000_PBA_16K
649 #define E1000_PBS_24K E1000_PBA_24K
655 #define MIN_NUM_XMITS 1000
658 #define E1000_SWSM_SMBI 0x00000001
659 #define E1000_SWSM_SWESMBI 0x00000002
660 #define E1000_SWSM_WMNG 0x00000004
661 #define E1000_SWSM_DRV_LOAD 0x00000008
664 #define E1000_ICR_TXDW 0x00000001
665 #define E1000_ICR_TXQE 0x00000002
666 #define E1000_ICR_LSC 0x00000004
667 #define E1000_ICR_RXSEQ 0x00000008
668 #define E1000_ICR_RXDMT0 0x00000010
669 #define E1000_ICR_RXO 0x00000040
670 #define E1000_ICR_RXT0 0x00000080
671 #define E1000_ICR_MDAC 0x00000200
672 #define E1000_ICR_RXCFG 0x00000400
673 #define E1000_ICR_GPI_EN0 0x00000800
674 #define E1000_ICR_GPI_EN1 0x00001000
675 #define E1000_ICR_GPI_EN2 0x00002000
676 #define E1000_ICR_GPI_EN3 0x00004000
677 #define E1000_ICR_TXD_LOW 0x00008000
678 #define E1000_ICR_SRPD 0x00010000
679 #define E1000_ICR_ACK 0x00020000
680 #define E1000_ICR_MNG 0x00040000
681 #define E1000_ICR_DOCK 0x00080000
682 #define E1000_ICR_INT_ASSERTED 0x80000000
683 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000
684 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000
685 #define E1000_ICR_HOST_ARB_PAR 0x00400000
686 #define E1000_ICR_PB_PAR 0x00800000
687 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000
688 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000
689 #define E1000_ICR_ALL_PARITY 0x03F00000
690 #define E1000_ICR_DSW 0x00000020
691 #define E1000_ICR_PHYINT 0x00001000
692 #define E1000_ICR_EPRST 0x00100000
695 #define E1000_EICR_RX_QUEUE0 0x00000001
696 #define E1000_EICR_RX_QUEUE1 0x00000002
697 #define E1000_EICR_RX_QUEUE2 0x00000004
698 #define E1000_EICR_RX_QUEUE3 0x00000008
699 #define E1000_EICR_TX_QUEUE0 0x00000100
700 #define E1000_EICR_TX_QUEUE1 0x00000200
701 #define E1000_EICR_TX_QUEUE2 0x00000400
702 #define E1000_EICR_TX_QUEUE3 0x00000800
703 #define E1000_EICR_TCP_TIMER 0x40000000
704 #define E1000_EICR_OTHER 0x80000000
706 #define E1000_TCPTIMER_KS 0x00000100
707 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200
708 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400
709 #define E1000_TCPTIMER_LOOP 0x00000800
717 #define POLL_IMS_ENABLE_MASK ( \
730 #define IMS_ENABLE_MASK ( \
738 #define E1000_IMS_TXDW E1000_ICR_TXDW
739 #define E1000_IMS_TXQE E1000_ICR_TXQE
740 #define E1000_IMS_LSC E1000_ICR_LSC
741 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
742 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
743 #define E1000_IMS_RXO E1000_ICR_RXO
744 #define E1000_IMS_RXT0 E1000_ICR_RXT0
745 #define E1000_IMS_MDAC E1000_ICR_MDAC
746 #define E1000_IMS_RXCFG E1000_ICR_RXCFG
747 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0
748 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1
749 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2
750 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3
751 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
752 #define E1000_IMS_SRPD E1000_ICR_SRPD
753 #define E1000_IMS_ACK E1000_ICR_ACK
754 #define E1000_IMS_MNG E1000_ICR_MNG
755 #define E1000_IMS_DOCK E1000_ICR_DOCK
756 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
757 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
758 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
759 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR
760 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
761 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
762 #define E1000_IMS_DSW E1000_ICR_DSW
763 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
764 #define E1000_IMS_EPRST E1000_ICR_EPRST
767 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0
768 #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1
769 #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2
770 #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3
771 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0
772 #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1
773 #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2
774 #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3
775 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER
776 #define E1000_EIMS_OTHER E1000_EICR_OTHER
779 #define E1000_ICS_TXDW E1000_ICR_TXDW
780 #define E1000_ICS_TXQE E1000_ICR_TXQE
781 #define E1000_ICS_LSC E1000_ICR_LSC
782 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
783 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
784 #define E1000_ICS_RXO E1000_ICR_RXO
785 #define E1000_ICS_RXT0 E1000_ICR_RXT0
786 #define E1000_ICS_MDAC E1000_ICR_MDAC
787 #define E1000_ICS_RXCFG E1000_ICR_RXCFG
788 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0
789 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1
790 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2
791 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3
792 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
793 #define E1000_ICS_SRPD E1000_ICR_SRPD
794 #define E1000_ICS_ACK E1000_ICR_ACK
795 #define E1000_ICS_MNG E1000_ICR_MNG
796 #define E1000_ICS_DOCK E1000_ICR_DOCK
797 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0
798 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0
799 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR
800 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR
801 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1
802 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1
803 #define E1000_ICS_DSW E1000_ICR_DSW
804 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
805 #define E1000_ICS_EPRST E1000_ICR_EPRST
808 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0
809 #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1
810 #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2
811 #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3
812 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0
813 #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1
814 #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2
815 #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3
816 #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER
817 #define E1000_EICS_OTHER E1000_EICR_OTHER
820 #define E1000_TXDCTL_PTHRESH 0x0000003F
821 #define E1000_TXDCTL_HTHRESH 0x00003F00
822 #define E1000_TXDCTL_WTHRESH 0x003F0000
823 #define E1000_TXDCTL_GRAN 0x01000000
824 #define E1000_TXDCTL_LWTHRESH 0xFE000000
825 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
826 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F
828 #define E1000_TXDCTL_COUNT_DESC 0x00400000
831 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
832 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
833 #define FLOW_CONTROL_TYPE 0x8808
836 #define VLAN_TAG_SIZE 4
837 #define E1000_VLAN_FILTER_TBL_SIZE 128
847 #define E1000_RAR_ENTRIES 15
848 #define E1000_RAH_AV 0x80000000
851 #define E1000_SUCCESS 0
852 #define E1000_ERR_NVM 1
853 #define E1000_ERR_PHY 2
854 #define E1000_ERR_CONFIG 3
855 #define E1000_ERR_PARAM 4
856 #define E1000_ERR_MAC_INIT 5
857 #define E1000_ERR_PHY_TYPE 6
858 #define E1000_ERR_RESET 9
859 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
860 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
861 #define E1000_BLK_PHY_RESET 12
862 #define E1000_ERR_SWFW_SYNC 13
863 #define E1000_NOT_IMPLEMENTED 14
866 #define FIBER_LINK_UP_LIMIT 50
867 #define COPPER_LINK_UP_LIMIT 10
868 #define PHY_AUTO_NEG_LIMIT 45
869 #define PHY_FORCE_LIMIT 20
871 #define MASTER_DISABLE_TIMEOUT 800
873 #define PHY_CFG_TIMEOUT 100
875 #define MDIO_OWNERSHIP_TIMEOUT 10
877 #define AUTO_READ_DONE_TIMEOUT 10
880 #define E1000_FCRTH_RTH 0x0000FFF8
881 #define E1000_FCRTH_XFCE 0x80000000
882 #define E1000_FCRTL_RTL 0x0000FFF8
883 #define E1000_FCRTL_XONE 0x80000000
886 #define E1000_TXCW_FD 0x00000020
887 #define E1000_TXCW_HD 0x00000040
888 #define E1000_TXCW_PAUSE 0x00000080
889 #define E1000_TXCW_ASM_DIR 0x00000100
890 #define E1000_TXCW_PAUSE_MASK 0x00000180
891 #define E1000_TXCW_RF 0x00003000
892 #define E1000_TXCW_NP 0x00008000
893 #define E1000_TXCW_CW 0x0000ffff
894 #define E1000_TXCW_TXC 0x40000000
895 #define E1000_TXCW_ANE 0x80000000
898 #define E1000_RXCW_CW 0x0000ffff
899 #define E1000_RXCW_NC 0x04000000
900 #define E1000_RXCW_IV 0x08000000
901 #define E1000_RXCW_CC 0x10000000
902 #define E1000_RXCW_C 0x20000000
903 #define E1000_RXCW_SYNCH 0x40000000
904 #define E1000_RXCW_ANC 0x80000000
907 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
908 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
909 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
910 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
911 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
912 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
914 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
915 E1000_GCR_RXDSCW_NO_SNOOP | \
916 E1000_GCR_RXDSCR_NO_SNOOP | \
917 E1000_GCR_TXD_NO_SNOOP | \
918 E1000_GCR_TXDSCW_NO_SNOOP | \
919 E1000_GCR_TXDSCR_NO_SNOOP)
922 #define MII_CR_SPEED_SELECT_MSB 0x0040
923 #define MII_CR_COLL_TEST_ENABLE 0x0080
924 #define MII_CR_FULL_DUPLEX 0x0100
925 #define MII_CR_RESTART_AUTO_NEG 0x0200
926 #define MII_CR_ISOLATE 0x0400
927 #define MII_CR_POWER_DOWN 0x0800
928 #define MII_CR_AUTO_NEG_EN 0x1000
929 #define MII_CR_SPEED_SELECT_LSB 0x2000
930 #define MII_CR_LOOPBACK 0x4000
931 #define MII_CR_RESET 0x8000
932 #define MII_CR_SPEED_1000 0x0040
933 #define MII_CR_SPEED_100 0x2000
934 #define MII_CR_SPEED_10 0x0000
937 #define MII_SR_EXTENDED_CAPS 0x0001
938 #define MII_SR_JABBER_DETECT 0x0002
939 #define MII_SR_LINK_STATUS 0x0004
940 #define MII_SR_AUTONEG_CAPS 0x0008
941 #define MII_SR_REMOTE_FAULT 0x0010
942 #define MII_SR_AUTONEG_COMPLETE 0x0020
943 #define MII_SR_PREAMBLE_SUPPRESS 0x0040
944 #define MII_SR_EXTENDED_STATUS 0x0100
945 #define MII_SR_100T2_HD_CAPS 0x0200
946 #define MII_SR_100T2_FD_CAPS 0x0400
947 #define MII_SR_10T_HD_CAPS 0x0800
948 #define MII_SR_10T_FD_CAPS 0x1000
949 #define MII_SR_100X_HD_CAPS 0x2000
950 #define MII_SR_100X_FD_CAPS 0x4000
951 #define MII_SR_100T4_CAPS 0x8000
954 #define NWAY_AR_SELECTOR_FIELD 0x0001
955 #define NWAY_AR_10T_HD_CAPS 0x0020
956 #define NWAY_AR_10T_FD_CAPS 0x0040
957 #define NWAY_AR_100TX_HD_CAPS 0x0080
958 #define NWAY_AR_100TX_FD_CAPS 0x0100
959 #define NWAY_AR_100T4_CAPS 0x0200
960 #define NWAY_AR_PAUSE 0x0400
961 #define NWAY_AR_ASM_DIR 0x0800
962 #define NWAY_AR_REMOTE_FAULT 0x2000
963 #define NWAY_AR_NEXT_PAGE 0x8000
966 #define NWAY_LPAR_SELECTOR_FIELD 0x0000
967 #define NWAY_LPAR_10T_HD_CAPS 0x0020
968 #define NWAY_LPAR_10T_FD_CAPS 0x0040
969 #define NWAY_LPAR_100TX_HD_CAPS 0x0080
970 #define NWAY_LPAR_100TX_FD_CAPS 0x0100
971 #define NWAY_LPAR_100T4_CAPS 0x0200
972 #define NWAY_LPAR_PAUSE 0x0400
973 #define NWAY_LPAR_ASM_DIR 0x0800
974 #define NWAY_LPAR_REMOTE_FAULT 0x2000
975 #define NWAY_LPAR_ACKNOWLEDGE 0x4000
976 #define NWAY_LPAR_NEXT_PAGE 0x8000
979 #define NWAY_ER_LP_NWAY_CAPS 0x0001
980 #define NWAY_ER_PAGE_RXD 0x0002
981 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004
982 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
983 #define NWAY_ER_PAR_DETECT_FAULT 0x0010
986 #define CR_1000T_ASYM_PAUSE 0x0080
987 #define CR_1000T_HD_CAPS 0x0100
988 #define CR_1000T_FD_CAPS 0x0200
989 #define CR_1000T_REPEATER_DTE 0x0400
991 #define CR_1000T_MS_VALUE 0x0800
993 #define CR_1000T_MS_ENABLE 0x1000
995 #define CR_1000T_TEST_MODE_NORMAL 0x0000
996 #define CR_1000T_TEST_MODE_1 0x2000
997 #define CR_1000T_TEST_MODE_2 0x4000
998 #define CR_1000T_TEST_MODE_3 0x6000
999 #define CR_1000T_TEST_MODE_4 0x8000
1002 #define SR_1000T_IDLE_ERROR_CNT 0x00FF
1003 #define SR_1000T_ASYM_PAUSE_DIR 0x0100
1004 #define SR_1000T_LP_HD_CAPS 0x0400
1005 #define SR_1000T_LP_FD_CAPS 0x0800
1006 #define SR_1000T_REMOTE_RX_STATUS 0x1000
1007 #define SR_1000T_LOCAL_RX_STATUS 0x2000
1008 #define SR_1000T_MS_CONFIG_RES 0x4000
1009 #define SR_1000T_MS_CONFIG_FAULT 0x8000
1011 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1015 #define PHY_CONTROL 0x00
1016 #define PHY_STATUS 0x01
1017 #define PHY_ID1 0x02
1018 #define PHY_ID2 0x03
1019 #define PHY_AUTONEG_ADV 0x04
1020 #define PHY_LP_ABILITY 0x05
1021 #define PHY_AUTONEG_EXP 0x06
1022 #define PHY_NEXT_PAGE_TX 0x07
1023 #define PHY_LP_NEXT_PAGE 0x08
1024 #define PHY_1000T_CTRL 0x09
1025 #define PHY_1000T_STATUS 0x0A
1026 #define PHY_EXT_STATUS 0x0F
1029 #define E1000_EECD_SK 0x00000001
1030 #define E1000_EECD_CS 0x00000002
1031 #define E1000_EECD_DI 0x00000004
1032 #define E1000_EECD_DO 0x00000008
1033 #define E1000_EECD_FWE_MASK 0x00000030
1034 #define E1000_EECD_FWE_DIS 0x00000010
1035 #define E1000_EECD_FWE_EN 0x00000020
1036 #define E1000_EECD_FWE_SHIFT 4
1037 #define E1000_EECD_REQ 0x00000040
1038 #define E1000_EECD_GNT 0x00000080
1039 #define E1000_EECD_PRES 0x00000100
1040 #define E1000_EECD_SIZE 0x00000200
1042 #define E1000_EECD_ADDR_BITS 0x00000400
1043 #define E1000_EECD_TYPE 0x00002000
1044 #define E1000_NVM_GRANT_ATTEMPTS 1000
1045 #define E1000_EECD_AUTO_RD 0x00000200
1046 #define E1000_EECD_SIZE_EX_MASK 0x00007800
1047 #define E1000_EECD_SIZE_EX_SHIFT 11
1048 #define E1000_EECD_NVADDS 0x00018000
1049 #define E1000_EECD_SELSHAD 0x00020000
1050 #define E1000_EECD_INITSRAM 0x00040000
1051 #define E1000_EECD_FLUPD 0x00080000
1052 #define E1000_EECD_AUPDEN 0x00100000
1053 #define E1000_EECD_SHADV 0x00200000
1054 #define E1000_EECD_SEC1VAL 0x00400000
1055 #define E1000_EECD_SECVAL_SHIFT 22
1057 #define E1000_NVM_SWDPIN0 0x0001
1058 #define E1000_NVM_LED_LOGIC 0x0020
1059 #define E1000_NVM_RW_REG_DATA 16
1060 #define E1000_NVM_RW_REG_DONE 2
1061 #define E1000_NVM_RW_REG_START 1
1062 #define E1000_NVM_RW_ADDR_SHIFT 2
1063 #define E1000_NVM_POLL_WRITE 1
1064 #define E1000_NVM_POLL_READ 0
1065 #define E1000_FLASH_UPDATES 2000
1068 #define NVM_COMPAT 0x0003
1069 #define NVM_ID_LED_SETTINGS 0x0004
1070 #define NVM_VERSION 0x0005
1071 #define NVM_SERDES_AMPLITUDE 0x0006
1072 #define NVM_PHY_CLASS_WORD 0x0007
1073 #define NVM_INIT_CONTROL1_REG 0x000A
1074 #define NVM_INIT_CONTROL2_REG 0x000F
1075 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1076 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1077 #define NVM_INIT_3GIO_3 0x001A
1078 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1079 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1080 #define NVM_CFG 0x0012
1081 #define NVM_FLASH_VERSION 0x0032
1082 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1083 #define NVM_CHECKSUM_REG 0x003F
1085 #define E1000_NVM_CFG_DONE_PORT_0 0x40000
1086 #define E1000_NVM_CFG_DONE_PORT_1 0x80000
1089 #define NVM_WORD0F_PAUSE_MASK 0x3000
1090 #define NVM_WORD0F_PAUSE 0x1000
1091 #define NVM_WORD0F_ASM_DIR 0x2000
1092 #define NVM_WORD0F_ANE 0x0800
1093 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1094 #define NVM_WORD0F_LPLU 0x0001
1097 #define NVM_WORD1A_ASPM_MASK 0x000C
1100 #define NVM_SUM 0xBABA
1102 #define NVM_MAC_ADDR_OFFSET 0
1103 #define NVM_PBA_OFFSET_0 8
1104 #define NVM_PBA_OFFSET_1 9
1105 #define NVM_RESERVED_WORD 0xFFFF
1106 #define NVM_PHY_CLASS_A 0x8000
1107 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1108 #define NVM_SIZE_MASK 0x1C00
1109 #define NVM_SIZE_SHIFT 10
1110 #define NVM_WORD_SIZE_BASE_SHIFT 6
1111 #define NVM_SWDPIO_EXT_SHIFT 4
1114 #define NVM_READ_OPCODE_MICROWIRE 0x6
1115 #define NVM_WRITE_OPCODE_MICROWIRE 0x5
1116 #define NVM_ERASE_OPCODE_MICROWIRE 0x7
1117 #define NVM_EWEN_OPCODE_MICROWIRE 0x13
1118 #define NVM_EWDS_OPCODE_MICROWIRE 0x10
1121 #define NVM_MAX_RETRY_SPI 5000
1122 #define NVM_READ_OPCODE_SPI 0x03
1123 #define NVM_WRITE_OPCODE_SPI 0x02
1124 #define NVM_A8_OPCODE_SPI 0x08
1125 #define NVM_WREN_OPCODE_SPI 0x06
1126 #define NVM_WRDI_OPCODE_SPI 0x04
1127 #define NVM_RDSR_OPCODE_SPI 0x05
1128 #define NVM_WRSR_OPCODE_SPI 0x01
1131 #define NVM_STATUS_RDY_SPI 0x01
1132 #define NVM_STATUS_WEN_SPI 0x02
1133 #define NVM_STATUS_BP0_SPI 0x04
1134 #define NVM_STATUS_BP1_SPI 0x08
1135 #define NVM_STATUS_WPEN_SPI 0x80
1138 #define ID_LED_RESERVED_0000 0x0000
1139 #define ID_LED_RESERVED_FFFF 0xFFFF
1140 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1141 (ID_LED_OFF1_OFF2 << 8) | \
1142 (ID_LED_DEF1_DEF2 << 4) | \
1144 #define ID_LED_DEF1_DEF2 0x1
1145 #define ID_LED_DEF1_ON2 0x2
1146 #define ID_LED_DEF1_OFF2 0x3
1147 #define ID_LED_ON1_DEF2 0x4
1148 #define ID_LED_ON1_ON2 0x5
1149 #define ID_LED_ON1_OFF2 0x6
1150 #define ID_LED_OFF1_DEF2 0x7
1151 #define ID_LED_OFF1_ON2 0x8
1152 #define ID_LED_OFF1_OFF2 0x9
1154 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1155 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1156 #define IGP_LED3_MODE 0x07000000
1159 #define PCIX_COMMAND_REGISTER 0xE6
1160 #define PCIX_STATUS_REGISTER_LO 0xE8
1161 #define PCIX_STATUS_REGISTER_HI 0xEA
1162 #define PCI_HEADER_TYPE_REGISTER 0x0E
1163 #define PCIE_LINK_STATUS 0x12
1165 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1166 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1167 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1168 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1169 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1170 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1171 #define PCIX_STATUS_LO_FUNC_MASK 0x7
1172 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1173 #define PCIE_LINK_WIDTH_MASK 0x3F0
1174 #define PCIE_LINK_WIDTH_SHIFT 4
1176 #ifndef ETH_ADDR_LEN
1177 #define ETH_ADDR_LEN 6
1180 #define PHY_REVISION_MASK 0xFFFFFFF0
1181 #define MAX_PHY_REG_ADDRESS 0x1F
1182 #define MAX_PHY_MULTI_PAGE_REG 0xF
1189 #define M88E1000_E_PHY_ID 0x01410C50
1190 #define M88E1000_I_PHY_ID 0x01410C30
1191 #define M88E1011_I_PHY_ID 0x01410C20
1192 #define IGP01E1000_I_PHY_ID 0x02A80380
1193 #define M88E1011_I_REV_4 0x04
1194 #define M88E1111_I_PHY_ID 0x01410CC0
1195 #define GG82563_E_PHY_ID 0x01410CA0
1196 #define IGP03E1000_E_PHY_ID 0x02A80390
1197 #define IFE_E_PHY_ID 0x02A80330
1198 #define IFE_PLUS_E_PHY_ID 0x02A80320
1199 #define IFE_C_E_PHY_ID 0x02A80310
1200 #define M88_VENDOR 0x0141
1203 #define M88E1000_PHY_SPEC_CTRL 0x10
1204 #define M88E1000_PHY_SPEC_STATUS 0x11
1205 #define M88E1000_INT_ENABLE 0x12
1206 #define M88E1000_INT_STATUS 0x13
1207 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14
1208 #define M88E1000_RX_ERR_CNTR 0x15
1210 #define M88E1000_PHY_EXT_CTRL 0x1A
1211 #define M88E1000_PHY_PAGE_SELECT 0x1D
1212 #define M88E1000_PHY_GEN_CONTROL 0x1E
1213 #define M88E1000_PHY_VCO_REG_BIT8 0x100
1214 #define M88E1000_PHY_VCO_REG_BIT11 0x800
1217 #define M88E1000_PSCR_JABBER_DISABLE 0x0001
1218 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
1219 #define M88E1000_PSCR_SQE_TEST 0x0004
1221 #define M88E1000_PSCR_CLK125_DISABLE 0x0010
1222 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1224 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
1226 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1228 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1233 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1235 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1236 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200
1237 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400
1238 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
1241 #define M88E1000_PSSR_JABBER 0x0001
1242 #define M88E1000_PSSR_REV_POLARITY 0x0002
1243 #define M88E1000_PSSR_DOWNSHIFT 0x0020
1244 #define M88E1000_PSSR_MDIX 0x0040
1252 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1253 #define M88E1000_PSSR_LINK 0x0400
1254 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800
1255 #define M88E1000_PSSR_PAGE_RCVD 0x1000
1256 #define M88E1000_PSSR_DPLX 0x2000
1257 #define M88E1000_PSSR_SPEED 0xC000
1258 #define M88E1000_PSSR_10MBS 0x0000
1259 #define M88E1000_PSSR_100MBS 0x4000
1260 #define M88E1000_PSSR_1000MBS 0x8000
1262 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1265 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000
1272 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1277 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1278 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1279 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1280 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1281 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1286 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1287 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1288 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1289 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1290 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1291 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060
1292 #define M88E1000_EPSCR_TX_CLK_25 0x0070
1293 #define M88E1000_EPSCR_TX_CLK_0 0x0000
1296 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1297 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
1298 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
1299 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
1300 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
1301 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1302 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
1303 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
1304 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
1311 #define GG82563_PAGE_SHIFT 5
1312 #define GG82563_REG(page, reg) \
1313 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1314 #define GG82563_MIN_ALT_REG 30
1317 #define GG82563_PHY_SPEC_CTRL \
1319 #define GG82563_PHY_SPEC_STATUS \
1321 #define GG82563_PHY_INT_ENABLE \
1323 #define GG82563_PHY_SPEC_STATUS_2 \
1325 #define GG82563_PHY_RX_ERR_CNTR \
1327 #define GG82563_PHY_PAGE_SELECT \
1329 #define GG82563_PHY_SPEC_CTRL_2 \
1331 #define GG82563_PHY_PAGE_SELECT_ALT \
1333 #define GG82563_PHY_TEST_CLK_CTRL \
1336 #define GG82563_PHY_MAC_SPEC_CTRL \
1338 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
1341 #define GG82563_PHY_DSP_DISTANCE \
1345 #define GG82563_PHY_KMRN_MODE_CTRL \
1346 GG82563_REG(193, 16)
1347 #define GG82563_PHY_PORT_RESET \
1348 GG82563_REG(193, 17)
1349 #define GG82563_PHY_REVISION_ID \
1350 GG82563_REG(193, 18)
1351 #define GG82563_PHY_DEVICE_ID \
1352 GG82563_REG(193, 19)
1353 #define GG82563_PHY_PWR_MGMT_CTRL \
1354 GG82563_REG(193, 20)
1355 #define GG82563_PHY_RATE_ADAPT_CTRL \
1356 GG82563_REG(193, 25)
1359 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1360 GG82563_REG(194, 16)
1361 #define GG82563_PHY_KMRN_CTRL \
1362 GG82563_REG(194, 17)
1363 #define GG82563_PHY_INBAND_CTRL \
1364 GG82563_REG(194, 18)
1365 #define GG82563_PHY_KMRN_DIAGNOSTIC \
1366 GG82563_REG(194, 19)
1367 #define GG82563_PHY_ACK_TIMEOUTS \
1368 GG82563_REG(194, 20)
1369 #define GG82563_PHY_ADV_ABILITY \
1370 GG82563_REG(194, 21)
1371 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1372 GG82563_REG(194, 23)
1373 #define GG82563_PHY_ADV_NEXT_PAGE \
1374 GG82563_REG(194, 24)
1375 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1376 GG82563_REG(194, 25)
1377 #define GG82563_PHY_KMRN_MISC \
1378 GG82563_REG(194, 26)
1381 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1382 #define E1000_MDIC_REG_MASK 0x001F0000
1383 #define E1000_MDIC_REG_SHIFT 16
1384 #define E1000_MDIC_PHY_MASK 0x03E00000
1385 #define E1000_MDIC_PHY_SHIFT 21
1386 #define E1000_MDIC_OP_WRITE 0x04000000
1387 #define E1000_MDIC_OP_READ 0x08000000
1388 #define E1000_MDIC_READY 0x10000000
1389 #define E1000_MDIC_INT_EN 0x20000000
1390 #define E1000_MDIC_ERROR 0x40000000
1393 #define E1000_GEN_CTL_READY 0x80000000
1394 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1395 #define E1000_GEN_POLL_TIMEOUT 640