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e1000_82575.h
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007 - 2008 Intel Corporation.
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RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#ifndef _E1000_82575_H_
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#define _E1000_82575_H_
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void
igb_update_mc_addr_list_82575(
struct
e1000_hw*, u8*, u32, u32, u32);
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extern
void
igb_shutdown_fiber_serdes_link_82575(
struct
e1000_hw *hw);
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extern
void
igb_rx_fifo_flush_82575(
struct
e1000_hw *hw);
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#define E1000_RAR_ENTRIES_82575 16
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#define E1000_RAR_ENTRIES_82576 24
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/* SRRCTL bit definitions */
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#define E1000_SRRCTL_BSIZEPKT_SHIFT 10
/* Shift _right_ */
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#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2
/* Shift _left_ */
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#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
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#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
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#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
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#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
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#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
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#define E1000_EICR_TX_QUEUE ( \
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E1000_EICR_TX_QUEUE0 | \
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E1000_EICR_TX_QUEUE1 | \
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E1000_EICR_TX_QUEUE2 | \
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E1000_EICR_TX_QUEUE3)
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#define E1000_EICR_RX_QUEUE ( \
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E1000_EICR_RX_QUEUE0 | \
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E1000_EICR_RX_QUEUE1 | \
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E1000_EICR_RX_QUEUE2 | \
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E1000_EICR_RX_QUEUE3)
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#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
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#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
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/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
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/* Receive Descriptor - Advanced */
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union
e1000_adv_rx_desc {
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struct
{
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__le64 pkt_addr;
/* Packet buffer address */
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__le64 hdr_addr;
/* Header buffer address */
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} read;
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struct
{
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struct
{
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struct
{
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__le16 pkt_info;
/* RSS type, Packet type */
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__le16 hdr_info;
/* Split Header,
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* header buffer length */
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} lo_dword;
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union
{
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__le32 rss;
/* RSS Hash */
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struct
{
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__le16 ip_id;
/* IP id */
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__le16 csum;
/* Packet Checksum */
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} csum_ip;
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} hi_dword;
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} lower;
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struct
{
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__le32 status_error;
/* ext status/error */
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__le16 length;
/* Packet length */
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__le16 vlan;
/* VLAN tag */
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} upper;
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} wb;
/* writeback */
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};
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#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
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#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
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/* RSS Hash results */
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/* RSS Packet Types as indicated in the receive descriptor */
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#define E1000_RXDADV_PKTTYPE_IPV4 0x00000010
/* IPV4 hdr present */
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#define E1000_RXDADV_PKTTYPE_TCP 0x00000100
/* TCP hdr present */
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/* Transmit Descriptor - Advanced */
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union
e1000_adv_tx_desc {
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struct
{
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__le64 buffer_addr;
/* Address of descriptor's data buf */
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__le32 cmd_type_len;
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__le32 olinfo_status;
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} read;
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struct
{
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__le64 rsvd;
/* Reserved */
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__le32 nxtseq_seed;
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__le32 status;
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} wb;
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};
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/* Adv Transmit Descriptor Config Masks */
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#define E1000_ADVTXD_DTYP_CTXT 0x00200000
/* Advanced Context Descriptor */
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#define E1000_ADVTXD_DTYP_DATA 0x00300000
/* Advanced Data Descriptor */
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#define E1000_ADVTXD_DCMD_IFCS 0x02000000
/* Insert FCS (Ethernet CRC) */
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#define E1000_ADVTXD_DCMD_DEXT 0x20000000
/* Descriptor extension (1=Adv) */
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#define E1000_ADVTXD_DCMD_VLE 0x40000000
/* VLAN pkt enable */
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#define E1000_ADVTXD_DCMD_TSE 0x80000000
/* TCP Seg enable */
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#define E1000_ADVTXD_PAYLEN_SHIFT 14
/* Adv desc PAYLEN shift */
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/* Context descriptors */
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struct
e1000_adv_tx_context_desc {
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__le32 vlan_macip_lens;
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__le32 seqnum_seed;
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__le32 type_tucmd_mlhl;
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__le32 mss_l4len_idx;
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};
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#define E1000_ADVTXD_MACLEN_SHIFT 9
/* Adv ctxt desc mac len shift */
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#define E1000_ADVTXD_TUCMD_IPV4 0x00000400
/* IP Packet Type: 1=IPv4 */
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#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800
/* L4 Packet TYPE of TCP */
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/* IPSec Encrypt Enable for ESP */
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#define E1000_ADVTXD_L4LEN_SHIFT 8
/* Adv ctxt L4LEN shift */
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#define E1000_ADVTXD_MSS_SHIFT 16
/* Adv ctxt MSS shift */
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/* Adv ctxt IPSec SA IDX mask */
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/* Adv ctxt IPSec ESP len mask */
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/* Additional Transmit Descriptor Control definitions */
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#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000
/* Enable specific Tx Queue */
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/* Tx Queue Arbitration Priority 0=low, 1=high */
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/* Additional Receive Descriptor Control definitions */
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#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000
/* Enable specific Rx Queue */
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/* Direct Cache Access (DCA) definitions */
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#define E1000_DCA_CTRL_DCA_ENABLE 0x00000000
/* DCA Enable */
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#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001
/* DCA Disable */
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#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00
/* DCA Mode CB1 */
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#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02
/* DCA Mode CB2 */
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#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F
/* Rx CPUID Mask */
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#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5)
/* DCA Rx Desc enable */
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#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6)
/* DCA Rx Desc header enable */
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#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7)
/* DCA Rx Desc payload enable */
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#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F
/* Tx CPUID Mask */
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#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5)
/* DCA Tx Desc enable */
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#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11)
/* Tx Desc writeback RO bit */
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/* Additional DCA related definitions, note change in position of CPUID */
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#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000
/* Tx CPUID Mask */
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#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000
/* Rx CPUID Mask */
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#define E1000_DCA_TXCTRL_CPUID_SHIFT 24
/* Tx CPUID now in the last byte */
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#define E1000_DCA_RXCTRL_CPUID_SHIFT 24
/* Rx CPUID now in the last byte */
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#endif
kernel
drivers
net
drivers
igb
e1000_82575.h
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