29 #ifndef _E1000_DEFINES_H_
30 #define _E1000_DEFINES_H_
33 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
34 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
38 #define E1000_WUC_PME_EN 0x00000002
41 #define E1000_WUFC_LNKC 0x00000001
42 #define E1000_WUFC_MAG 0x00000002
43 #define E1000_WUFC_EX 0x00000004
44 #define E1000_WUFC_MC 0x00000008
45 #define E1000_WUFC_BC 0x00000010
46 #define E1000_WUFC_ARP 0x00000020
47 #define E1000_WUFC_IPV4 0x00000040
48 #define E1000_WUFC_IPV6 0x00000080
49 #define E1000_WUFC_FLX0 0x00010000
50 #define E1000_WUFC_FLX1 0x00020000
51 #define E1000_WUFC_FLX2 0x00040000
52 #define E1000_WUFC_FLX3 0x00080000
53 #define E1000_WUFC_FLX_FILTERS 0x000F0000
60 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
63 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
67 #define E1000_CTRL_EXT_GPI1_EN 0x00000002
68 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010
69 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020
70 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080
71 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100
72 #define E1000_CTRL_EXT_EE_RST 0x00002000
73 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
74 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
75 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
76 #define E1000_CTRL_EXT_EIAME 0x01000000
77 #define E1000_CTRL_EXT_IRCA 0x00000001
80 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
85 #define E1000_CTRL_EXT_PBA_CLR 0x80000000
86 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
87 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
88 #define E1000_I2CCMD_OPCODE_READ 0x08000000
89 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
90 #define E1000_I2CCMD_READY 0x20000000
91 #define E1000_I2CCMD_ERROR 0x80000000
92 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
93 #define E1000_I2CCMD_PHY_TIMEOUT 200
94 #define E1000_IVAR_VALID 0x80
95 #define E1000_GPIE_NSICR 0x00000001
96 #define E1000_GPIE_MSIX_MODE 0x00000010
97 #define E1000_GPIE_EIAME 0x40000000
98 #define E1000_GPIE_PBA 0x80000000
101 #define E1000_RXD_STAT_DD 0x01
102 #define E1000_RXD_STAT_EOP 0x02
103 #define E1000_RXD_STAT_IXSM 0x04
104 #define E1000_RXD_STAT_VP 0x08
105 #define E1000_RXD_STAT_UDPCS 0x10
106 #define E1000_RXD_STAT_TCPCS 0x20
107 #define E1000_RXD_STAT_DYNINT 0x800
108 #define E1000_RXD_ERR_CE 0x01
109 #define E1000_RXD_ERR_SE 0x02
110 #define E1000_RXD_ERR_SEQ 0x04
111 #define E1000_RXD_ERR_CXE 0x10
112 #define E1000_RXD_ERR_RXE 0x80
113 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF
115 #define E1000_RXDEXT_STATERR_CE 0x01000000
116 #define E1000_RXDEXT_STATERR_SE 0x02000000
117 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
118 #define E1000_RXDEXT_STATERR_CXE 0x10000000
119 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
120 #define E1000_RXDEXT_STATERR_IPE 0x40000000
121 #define E1000_RXDEXT_STATERR_RXE 0x80000000
124 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
127 E1000_RXD_ERR_SEQ | \
128 E1000_RXD_ERR_CXE | \
132 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
133 E1000_RXDEXT_STATERR_CE | \
134 E1000_RXDEXT_STATERR_SE | \
135 E1000_RXDEXT_STATERR_SEQ | \
136 E1000_RXDEXT_STATERR_CXE | \
137 E1000_RXDEXT_STATERR_RXE)
139 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
140 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
141 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
142 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
143 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
147 #define E1000_MANC_SMBUS_EN 0x00000001
148 #define E1000_MANC_ASF_EN 0x00000002
149 #define E1000_MANC_ARP_EN 0x00002000
151 #define E1000_MANC_RCV_TCO_EN 0x00020000
152 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
154 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
156 #define E1000_MANC_EN_MNG2HOST 0x00200000
161 #define E1000_RCTL_EN 0x00000002
162 #define E1000_RCTL_SBP 0x00000004
163 #define E1000_RCTL_UPE 0x00000008
164 #define E1000_RCTL_MPE 0x00000010
165 #define E1000_RCTL_LPE 0x00000020
166 #define E1000_RCTL_LBM_NO 0x00000000
167 #define E1000_RCTL_LBM_MAC 0x00000040
168 #define E1000_RCTL_LBM_TCVR 0x000000C0
169 #define E1000_RCTL_RDMTS_HALF 0x00000000
170 #define E1000_RCTL_MO_SHIFT 12
171 #define E1000_RCTL_BAM 0x00008000
172 #define E1000_RCTL_SZ_2048 0x00000000
173 #define E1000_RCTL_SZ_1024 0x00010000
174 #define E1000_RCTL_SZ_512 0x00020000
175 #define E1000_RCTL_SZ_256 0x00030000
176 #define E1000_RCTL_VFE 0x00040000
177 #define E1000_RCTL_CFIEN 0x00080000
178 #define E1000_RCTL_SECRC 0x04000000
197 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
198 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
199 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
200 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
202 #define E1000_PSRCTL_BSIZE0_SHIFT 7
203 #define E1000_PSRCTL_BSIZE1_SHIFT 2
204 #define E1000_PSRCTL_BSIZE2_SHIFT 6
205 #define E1000_PSRCTL_BSIZE3_SHIFT 14
208 #define E1000_SWFW_EEP_SM 0x1
209 #define E1000_SWFW_PHY0_SM 0x2
210 #define E1000_SWFW_PHY1_SM 0x4
214 #define E1000_CTRL_FD 0x00000001
215 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
216 #define E1000_CTRL_LRST 0x00000008
217 #define E1000_CTRL_ASDE 0x00000020
218 #define E1000_CTRL_SLU 0x00000040
219 #define E1000_CTRL_ILOS 0x00000080
220 #define E1000_CTRL_SPD_SEL 0x00000300
221 #define E1000_CTRL_SPD_100 0x00000100
222 #define E1000_CTRL_SPD_1000 0x00000200
223 #define E1000_CTRL_FRCSPD 0x00000800
224 #define E1000_CTRL_FRCDPX 0x00001000
228 #define E1000_CTRL_SWDPIN0 0x00040000
229 #define E1000_CTRL_SWDPIN1 0x00080000
230 #define E1000_CTRL_SWDPIN2 0x00100000
231 #define E1000_CTRL_SWDPIN3 0x00200000
232 #define E1000_CTRL_SWDPIO0 0x00400000
233 #define E1000_CTRL_SWDPIO2 0x01000000
234 #define E1000_CTRL_SWDPIO3 0x02000000
235 #define E1000_CTRL_RST 0x04000000
236 #define E1000_CTRL_RFCE 0x08000000
237 #define E1000_CTRL_TFCE 0x10000000
238 #define E1000_CTRL_VME 0x40000000
239 #define E1000_CTRL_PHY_RST 0x80000000
241 #define E1000_CTRL_I2C_ENA 0x02000000
247 #define E1000_CONNSW_ENRGSRC 0x4
248 #define E1000_PCS_CFG_PCS_EN 8
249 #define E1000_PCS_LCTL_FLV_LINK_UP 1
250 #define E1000_PCS_LCTL_FSV_100 2
251 #define E1000_PCS_LCTL_FSV_1000 4
252 #define E1000_PCS_LCTL_FDV_FULL 8
253 #define E1000_PCS_LCTL_FSD 0x10
254 #define E1000_PCS_LCTL_FORCE_LINK 0x20
255 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
256 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
257 #define E1000_PCS_LCTL_AN_RESTART 0x20000
258 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
259 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
261 #define E1000_PCS_LSTS_LINK_OK 1
262 #define E1000_PCS_LSTS_SPEED_100 2
263 #define E1000_PCS_LSTS_SPEED_1000 4
264 #define E1000_PCS_LSTS_DUPLEX_FULL 8
265 #define E1000_PCS_LSTS_SYNK_OK 0x10
268 #define E1000_STATUS_FD 0x00000001
269 #define E1000_STATUS_LU 0x00000002
270 #define E1000_STATUS_FUNC_MASK 0x0000000C
271 #define E1000_STATUS_FUNC_SHIFT 2
272 #define E1000_STATUS_FUNC_1 0x00000004
273 #define E1000_STATUS_TXOFF 0x00000010
274 #define E1000_STATUS_SPEED_100 0x00000040
275 #define E1000_STATUS_SPEED_1000 0x00000080
278 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
284 #define SPEED_100 100
285 #define SPEED_1000 1000
286 #define HALF_DUPLEX 1
287 #define FULL_DUPLEX 2
290 #define ADVERTISE_10_HALF 0x0001
291 #define ADVERTISE_10_FULL 0x0002
292 #define ADVERTISE_100_HALF 0x0004
293 #define ADVERTISE_100_FULL 0x0008
294 #define ADVERTISE_1000_HALF 0x0010
295 #define ADVERTISE_1000_FULL 0x0020
298 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
299 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
301 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
302 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
303 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
304 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
305 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
307 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
309 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
312 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
313 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
314 #define E1000_LEDCTL_LED0_IVRT 0x00000040
315 #define E1000_LEDCTL_LED0_BLINK 0x00000080
317 #define E1000_LEDCTL_MODE_LED_ON 0xE
318 #define E1000_LEDCTL_MODE_LED_OFF 0xF
321 #define E1000_TXD_POPTS_IXSM 0x01
322 #define E1000_TXD_POPTS_TXSM 0x02
323 #define E1000_TXD_CMD_EOP 0x01000000
324 #define E1000_TXD_CMD_IFCS 0x02000000
325 #define E1000_TXD_CMD_RS 0x08000000
326 #define E1000_TXD_CMD_DEXT 0x20000000
327 #define E1000_TXD_STAT_DD 0x00000001
331 #define E1000_TCTL_EN 0x00000002
332 #define E1000_TCTL_PSP 0x00000008
333 #define E1000_TCTL_CT 0x00000ff0
334 #define E1000_TCTL_COLD 0x003ff000
335 #define E1000_TCTL_RTLC 0x01000000
340 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
343 #define E1000_RXCSUM_TUOFL 0x00000200
344 #define E1000_RXCSUM_IPPCSE 0x00001000
345 #define E1000_RXCSUM_PCSD 0x00002000
348 #define E1000_RFCTL_LEF 0x00040000
351 #define E1000_COLLISION_THRESHOLD 15
352 #define E1000_CT_SHIFT 4
353 #define E1000_COLLISION_DISTANCE 63
354 #define E1000_COLD_SHIFT 12
357 #define ETHERNET_IEEE_VLAN_TYPE 0x8100
359 #define MAX_JUMBO_FRAME_SIZE 0x3F00
362 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
365 #define E1000_PBA_16K 0x0010
366 #define E1000_PBA_24K 0x0018
367 #define E1000_PBA_34K 0x0022
368 #define E1000_PBA_64K 0x0040
374 #define MIN_NUM_XMITS 1000
377 #define E1000_SWSM_SMBI 0x00000001
378 #define E1000_SWSM_SWESMBI 0x00000002
381 #define E1000_ICR_TXDW 0x00000001
382 #define E1000_ICR_TXQE 0x00000002
383 #define E1000_ICR_LSC 0x00000004
384 #define E1000_ICR_RXSEQ 0x00000008
385 #define E1000_ICR_RXDMT0 0x00000010
386 #define E1000_ICR_RXO 0x00000040
387 #define E1000_ICR_RXT0 0x00000080
388 #define E1000_ICR_MDAC 0x00000200
389 #define E1000_ICR_RXCFG 0x00000400
390 #define E1000_ICR_GPI_EN0 0x00000800
391 #define E1000_ICR_GPI_EN1 0x00001000
392 #define E1000_ICR_GPI_EN2 0x00002000
393 #define E1000_ICR_GPI_EN3 0x00004000
394 #define E1000_ICR_TXD_LOW 0x00008000
395 #define E1000_ICR_SRPD 0x00010000
396 #define E1000_ICR_ACK 0x00020000
397 #define E1000_ICR_MNG 0x00040000
398 #define E1000_ICR_DOCK 0x00080000
400 #define E1000_ICR_INT_ASSERTED 0x80000000
402 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000
404 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000
406 #define E1000_ICR_HOST_ARB_PAR 0x00400000
407 #define E1000_ICR_PB_PAR 0x00800000
409 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000
411 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000
413 #define E1000_ICR_DSW 0x00000020
415 #define E1000_ICR_PHYINT 0x00001000
416 #define E1000_ICR_EPRST 0x00100000
419 #define E1000_EICR_RX_QUEUE0 0x00000001
420 #define E1000_EICR_RX_QUEUE1 0x00000002
421 #define E1000_EICR_RX_QUEUE2 0x00000004
422 #define E1000_EICR_RX_QUEUE3 0x00000008
423 #define E1000_EICR_TX_QUEUE0 0x00000100
424 #define E1000_EICR_TX_QUEUE1 0x00000200
425 #define E1000_EICR_TX_QUEUE2 0x00000400
426 #define E1000_EICR_TX_QUEUE3 0x00000800
427 #define E1000_EICR_TCP_TIMER 0x40000000
428 #define E1000_EICR_OTHER 0x80000000
440 #define IMS_ENABLE_MASK ( \
448 #define E1000_IMS_TXDW E1000_ICR_TXDW
449 #define E1000_IMS_LSC E1000_ICR_LSC
450 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
451 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
452 #define E1000_IMS_RXT0 E1000_ICR_RXT0
455 #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER
456 #define E1000_EIMS_OTHER E1000_EICR_OTHER
459 #define E1000_ICS_LSC E1000_ICR_LSC
460 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
468 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
469 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
470 #define FLOW_CONTROL_TYPE 0x8808
473 #define VLAN_TAG_SIZE 4
474 #define E1000_VLAN_FILTER_TBL_SIZE 128
484 #define E1000_RAH_AV 0x80000000
487 #define E1000_ERR_NVM 1
488 #define E1000_ERR_PHY 2
489 #define E1000_ERR_CONFIG 3
490 #define E1000_ERR_PARAM 4
491 #define E1000_ERR_MAC_INIT 5
492 #define E1000_ERR_RESET 9
493 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
494 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
495 #define E1000_BLK_PHY_RESET 12
496 #define E1000_ERR_SWFW_SYNC 13
497 #define E1000_NOT_IMPLEMENTED 14
500 #define COPPER_LINK_UP_LIMIT 10
501 #define PHY_AUTO_NEG_LIMIT 45
502 #define PHY_FORCE_LIMIT 20
504 #define MASTER_DISABLE_TIMEOUT 800
506 #define PHY_CFG_TIMEOUT 100
509 #define AUTO_READ_DONE_TIMEOUT 10
512 #define E1000_FCRTL_XONE 0x80000000
515 #define E1000_TXCW_ANE 0x80000000
520 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
521 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
522 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
523 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
524 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
525 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
527 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
528 E1000_GCR_RXDSCW_NO_SNOOP | \
529 E1000_GCR_RXDSCR_NO_SNOOP | \
530 E1000_GCR_TXD_NO_SNOOP | \
531 E1000_GCR_TXDSCW_NO_SNOOP | \
532 E1000_GCR_TXDSCR_NO_SNOOP)
535 #define MII_CR_FULL_DUPLEX 0x0100
536 #define MII_CR_RESTART_AUTO_NEG 0x0200
537 #define MII_CR_POWER_DOWN 0x0800
538 #define MII_CR_AUTO_NEG_EN 0x1000
539 #define MII_CR_LOOPBACK 0x4000
540 #define MII_CR_RESET 0x8000
541 #define MII_CR_SPEED_1000 0x0040
542 #define MII_CR_SPEED_100 0x2000
543 #define MII_CR_SPEED_10 0x0000
546 #define MII_SR_LINK_STATUS 0x0004
547 #define MII_SR_AUTONEG_COMPLETE 0x0020
550 #define NWAY_AR_10T_HD_CAPS 0x0020
551 #define NWAY_AR_10T_FD_CAPS 0x0040
552 #define NWAY_AR_100TX_HD_CAPS 0x0080
553 #define NWAY_AR_100TX_FD_CAPS 0x0100
554 #define NWAY_AR_PAUSE 0x0400
555 #define NWAY_AR_ASM_DIR 0x0800
558 #define NWAY_LPAR_PAUSE 0x0400
559 #define NWAY_LPAR_ASM_DIR 0x0800
564 #define CR_1000T_HD_CAPS 0x0100
565 #define CR_1000T_FD_CAPS 0x0200
566 #define CR_1000T_MS_VALUE 0x0800
568 #define CR_1000T_MS_ENABLE 0x1000
572 #define SR_1000T_REMOTE_RX_STATUS 0x1000
573 #define SR_1000T_LOCAL_RX_STATUS 0x2000
578 #define PHY_CONTROL 0x00
579 #define PHY_STATUS 0x01
582 #define PHY_AUTONEG_ADV 0x04
583 #define PHY_LP_ABILITY 0x05
584 #define PHY_1000T_CTRL 0x09
585 #define PHY_1000T_STATUS 0x0A
588 #define E1000_EECD_SK 0x00000001
589 #define E1000_EECD_CS 0x00000002
590 #define E1000_EECD_DI 0x00000004
591 #define E1000_EECD_DO 0x00000008
592 #define E1000_EECD_REQ 0x00000040
593 #define E1000_EECD_GNT 0x00000080
594 #define E1000_EECD_PRES 0x00000100
596 #define E1000_EECD_ADDR_BITS 0x00000400
597 #define E1000_NVM_GRANT_ATTEMPTS 1000
598 #define E1000_EECD_AUTO_RD 0x00000200
599 #define E1000_EECD_SIZE_EX_MASK 0x00007800
600 #define E1000_EECD_SIZE_EX_SHIFT 11
603 #define E1000_NVM_RW_REG_DATA 16
604 #define E1000_NVM_RW_REG_DONE 2
605 #define E1000_NVM_RW_REG_START 1
606 #define E1000_NVM_RW_ADDR_SHIFT 2
607 #define E1000_NVM_POLL_READ 0
610 #define NVM_ID_LED_SETTINGS 0x0004
612 #define NVM_INIT_CONTROL2_REG 0x000F
613 #define NVM_INIT_CONTROL3_PORT_A 0x0024
614 #define NVM_ALT_MAC_ADDR_PTR 0x0037
615 #define NVM_CHECKSUM_REG 0x003F
617 #define E1000_NVM_CFG_DONE_PORT_0 0x40000
618 #define E1000_NVM_CFG_DONE_PORT_1 0x80000
621 #define NVM_WORD0F_PAUSE_MASK 0x3000
622 #define NVM_WORD0F_ASM_DIR 0x2000
627 #define NVM_SUM 0xBABA
629 #define NVM_PBA_OFFSET_0 8
630 #define NVM_PBA_OFFSET_1 9
631 #define NVM_WORD_SIZE_BASE_SHIFT 6
636 #define NVM_MAX_RETRY_SPI 5000
637 #define NVM_WRITE_OPCODE_SPI 0x02
638 #define NVM_A8_OPCODE_SPI 0x08
639 #define NVM_WREN_OPCODE_SPI 0x06
640 #define NVM_RDSR_OPCODE_SPI 0x05
643 #define NVM_STATUS_RDY_SPI 0x01
646 #define ID_LED_RESERVED_0000 0x0000
647 #define ID_LED_RESERVED_FFFF 0xFFFF
648 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
649 (ID_LED_OFF1_OFF2 << 8) | \
650 (ID_LED_DEF1_DEF2 << 4) | \
652 #define ID_LED_DEF1_DEF2 0x1
653 #define ID_LED_DEF1_ON2 0x2
654 #define ID_LED_DEF1_OFF2 0x3
655 #define ID_LED_ON1_DEF2 0x4
656 #define ID_LED_ON1_ON2 0x5
657 #define ID_LED_ON1_OFF2 0x6
658 #define ID_LED_OFF1_DEF2 0x7
659 #define ID_LED_OFF1_ON2 0x8
660 #define ID_LED_OFF1_OFF2 0x9
662 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
663 #define IGP_ACTIVITY_LED_ENABLE 0x0300
664 #define IGP_LED3_MODE 0x07000000
667 #define PCI_HEADER_TYPE_REGISTER 0x0E
668 #define PCIE_LINK_STATUS 0x12
670 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
671 #define PCIE_LINK_WIDTH_MASK 0x3F0
672 #define PCIE_LINK_WIDTH_SHIFT 4
674 #define PHY_REVISION_MASK 0xFFFFFFF0
675 #define MAX_PHY_REG_ADDRESS 0x1F
676 #define MAX_PHY_MULTI_PAGE_REG 0xF
683 #define M88E1111_I_PHY_ID 0x01410CC0
684 #define IGP03E1000_E_PHY_ID 0x02A80390
685 #define M88_VENDOR 0x0141
688 #define M88E1000_PHY_SPEC_CTRL 0x10
689 #define M88E1000_PHY_SPEC_STATUS 0x11
690 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14
692 #define M88E1000_PHY_PAGE_SELECT 0x1D
693 #define M88E1000_PHY_GEN_CONTROL 0x1E
696 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
698 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
700 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
702 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
704 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
710 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
713 #define M88E1000_PSSR_REV_POLARITY 0x0002
714 #define M88E1000_PSSR_DOWNSHIFT 0x0020
715 #define M88E1000_PSSR_MDIX 0x0040
723 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
724 #define M88E1000_PSSR_SPEED 0xC000
725 #define M88E1000_PSSR_1000MBS 0x8000
727 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
740 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
741 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
746 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
747 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
748 #define M88E1000_EPSCR_TX_CLK_25 0x0070
751 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
752 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
755 #define E1000_MDIC_REG_SHIFT 16
756 #define E1000_MDIC_PHY_SHIFT 21
757 #define E1000_MDIC_OP_WRITE 0x04000000
758 #define E1000_MDIC_OP_READ 0x08000000
759 #define E1000_MDIC_READY 0x10000000
760 #define E1000_MDIC_ERROR 0x40000000
763 #define E1000_GEN_CTL_READY 0x80000000
764 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
765 #define E1000_GEN_POLL_TIMEOUT 640