Xenomai  3.0-rc7
e1000_phy.h
1 /*******************************************************************************
2 
3  Intel(R) Gigabit Ethernet Linux driver
4  Copyright(c) 2007 Intel Corporation.
5  RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
6 
7  This program is free software; you can redistribute it and/or modify it
8  under the terms and conditions of the GNU General Public License,
9  version 2, as published by the Free Software Foundation.
10 
11  This program is distributed in the hope it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc.,
18  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 
20  The full GNU General Public License is included in this distribution in
21  the file called "COPYING".
22 
23  Contact Information:
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_PHY_H_
30 #define _E1000_PHY_H_
31 
32 struct e1000_hw;
33 
34 enum e1000_ms_type {
35  e1000_ms_hw_default = 0,
36  e1000_ms_force_master,
37  e1000_ms_force_slave,
38  e1000_ms_auto
39 };
40 
41 enum e1000_smart_speed {
42  e1000_smart_speed_default = 0,
43  e1000_smart_speed_on,
44  e1000_smart_speed_off
45 };
46 
47 s32 igb_check_downshift(struct e1000_hw *hw);
48 s32 igb_check_reset_block(struct e1000_hw *hw);
49 s32 igb_copper_link_autoneg(struct e1000_hw *hw);
50 s32 igb_phy_force_speed_duplex(struct e1000_hw *hw);
51 s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
52 s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
53 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
54 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
55 s32 igb_get_cable_length_m88(struct e1000_hw *hw);
56 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
57 s32 igb_get_phy_id(struct e1000_hw *hw);
58 s32 igb_get_phy_info_igp(struct e1000_hw *hw);
59 s32 igb_get_phy_info_m88(struct e1000_hw *hw);
60 s32 igb_phy_sw_reset(struct e1000_hw *hw);
61 s32 igb_phy_hw_reset(struct e1000_hw *hw);
62 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
63 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
64 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
65 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
66  u32 usec_interval, bool *success);
67 s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
68 
69 /* IGP01E1000 Specific Registers */
70 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
71 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
72 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
73 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
74 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
75 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
76 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
77 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
78 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
79 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
80 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
81 
82 /* Enable flexible speed on link-up */
83 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
84 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
85 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
86 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
87 #define IGP01E1000_PSSR_MDIX 0x0008
88 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
89 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
90 #define IGP02E1000_PHY_CHANNEL_NUM 4
91 #define IGP02E1000_PHY_AGC_A 0x11B1
92 #define IGP02E1000_PHY_AGC_B 0x12B1
93 #define IGP02E1000_PHY_AGC_C 0x14B1
94 #define IGP02E1000_PHY_AGC_D 0x18B1
95 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
96 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
97 #define IGP02E1000_AGC_RANGE 15
98 
99 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
100 
101 #endif