Xenomai  3.0-rc7
e1000_82575.h
1 /*******************************************************************************
2 
3  Intel(R) Gigabit Ethernet Linux driver
4  Copyright(c) 2007 - 2008 Intel Corporation.
5  RTnet port 2009 Vladimir Zapolskiy <vladimir.zapolskiy@siemens.com>
6 
7  This program is free software; you can redistribute it and/or modify it
8  under the terms and conditions of the GNU General Public License,
9  version 2, as published by the Free Software Foundation.
10 
11  This program is distributed in the hope it will be useful, but WITHOUT
12  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14  more details.
15 
16  You should have received a copy of the GNU General Public License along with
17  this program; if not, write to the Free Software Foundation, Inc.,
18  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 
20  The full GNU General Public License is included in this distribution in
21  the file called "COPYING".
22 
23  Contact Information:
24  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 
27 *******************************************************************************/
28 
29 #ifndef _E1000_82575_H_
30 #define _E1000_82575_H_
31 
32 void igb_update_mc_addr_list_82575(struct e1000_hw*, u8*, u32, u32, u32);
33 extern void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
34 extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
35 
36 #define E1000_RAR_ENTRIES_82575 16
37 #define E1000_RAR_ENTRIES_82576 24
38 
39 /* SRRCTL bit definitions */
40 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
41 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
42 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
43 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
44 
45 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
46 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
47 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
48 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
49 
50 #define E1000_EICR_TX_QUEUE ( \
51  E1000_EICR_TX_QUEUE0 | \
52  E1000_EICR_TX_QUEUE1 | \
53  E1000_EICR_TX_QUEUE2 | \
54  E1000_EICR_TX_QUEUE3)
55 
56 #define E1000_EICR_RX_QUEUE ( \
57  E1000_EICR_RX_QUEUE0 | \
58  E1000_EICR_RX_QUEUE1 | \
59  E1000_EICR_RX_QUEUE2 | \
60  E1000_EICR_RX_QUEUE3)
61 
62 #define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
63 #define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
64 
65 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
66 
67 /* Receive Descriptor - Advanced */
68 union e1000_adv_rx_desc {
69  struct {
70  __le64 pkt_addr; /* Packet buffer address */
71  __le64 hdr_addr; /* Header buffer address */
72  } read;
73  struct {
74  struct {
75  struct {
76  __le16 pkt_info; /* RSS type, Packet type */
77  __le16 hdr_info; /* Split Header,
78  * header buffer length */
79  } lo_dword;
80  union {
81  __le32 rss; /* RSS Hash */
82  struct {
83  __le16 ip_id; /* IP id */
84  __le16 csum; /* Packet Checksum */
85  } csum_ip;
86  } hi_dword;
87  } lower;
88  struct {
89  __le32 status_error; /* ext status/error */
90  __le16 length; /* Packet length */
91  __le16 vlan; /* VLAN tag */
92  } upper;
93  } wb; /* writeback */
94 };
95 
96 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
97 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
98 
99 /* RSS Hash results */
100 
101 /* RSS Packet Types as indicated in the receive descriptor */
102 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
103 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
104 
105 /* Transmit Descriptor - Advanced */
106 union e1000_adv_tx_desc {
107  struct {
108  __le64 buffer_addr; /* Address of descriptor's data buf */
109  __le32 cmd_type_len;
110  __le32 olinfo_status;
111  } read;
112  struct {
113  __le64 rsvd; /* Reserved */
114  __le32 nxtseq_seed;
115  __le32 status;
116  } wb;
117 };
118 
119 /* Adv Transmit Descriptor Config Masks */
120 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
121 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
122 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
123 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
124 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
125 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
126 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
127 
128 /* Context descriptors */
129 struct e1000_adv_tx_context_desc {
130  __le32 vlan_macip_lens;
131  __le32 seqnum_seed;
132  __le32 type_tucmd_mlhl;
133  __le32 mss_l4len_idx;
134 };
135 
136 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
137 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
138 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
139 /* IPSec Encrypt Enable for ESP */
140 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
141 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
142 /* Adv ctxt IPSec SA IDX mask */
143 /* Adv ctxt IPSec ESP len mask */
144 
145 /* Additional Transmit Descriptor Control definitions */
146 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
147 /* Tx Queue Arbitration Priority 0=low, 1=high */
148 
149 /* Additional Receive Descriptor Control definitions */
150 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
151 
152 /* Direct Cache Access (DCA) definitions */
153 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
154 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
155 
156 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
157 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
158 
159 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
160 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
161 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
162 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
163 
164 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
165 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
166 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
167 
168 /* Additional DCA related definitions, note change in position of CPUID */
169 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
170 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
171 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
172 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
173 
174 #endif