/*
 *	FILE    	s3c2400.h
 *
 *	Version 	1.2
 *	Author  	Copyright (c) Marc A. Viredaz, 1998
 *	        	DEC Western Research Laboratory, Palo Alto, CA
 *	Date    	January 1998 (April 1997)
 *	System  	StrongARM SA-1100
 *	Language	C or ARM Assembly
 *	Purpose 	Definition of constants related to the StrongARM
 *	        	SA-1100 microprocessor (Advanced RISC Machine (ARM)
 *	        	architecture version 4). This file is based on the
 *	        	StrongARM SA-1100 data sheet version 2.2.
 *
 *	        	Language-specific definitions are selected by the
 *	        	macro "LANGUAGE", which should be defined as either
 *	        	"C" (default) or "Assembly".
 */


/* Be sure that virtual mapping is defined right */
#ifndef __ASM_ARCH_HARDWARE_H
#error You must include hardware.h not s3c2400.h
#endif


#ifndef LANGUAGE
#define LANGUAGE	C
#endif /* !defined (LANGUAGE) */

#ifndef io_p2v
#define io_p2v(PhAdd)	(PhAdd)
#endif /* !defined (io_p2v) */

#include <asm/arch/bitfield.h>

#define C       	0
#define Assembly	1


/*
 * Universal Asynchronous Receiver/Transmitter (UART) control registers
 *
 */

#define SERBASE	0xf5000000

/* Register offsets */
#define ULCON		0x00
#define UCON		0x04
#define UFCON		0x08
#define UMCON		0x0c
#define UTRSTAT		0x10
#define UERSTAT		0x14
#define UFSTAT		0x18
#define UMSTAT		0x1c
#define UTXH		0x20
#define URXH		0x24
#define UBRDIV		0x28

/* ULCON bits - Line Control */
#define ULCON_5BITS	0x00
#define ULCON_6BITS	0x01
#define ULCON_7BITS	0x02
#define ULCON_8BITS	0x03
#define ULCON_1STOP	0x00
#define ULCON_2STOP	(1 << 2)
#define ULCON_NOPAR	0x00
#define ULCON_ODDPAR	(4 << 3)
#define ULCON_EVENPAR	(5 << 3)
#define ULCON_PARFORCE1	(6 << 3) /* parity forced/checked as 1 */
#define ULCON_PARFORCE0	(7 << 3) /* parity forced/checked as 0 */
#define ULCON_NORMAL	0x00
#define ULCON_IR	(1 << 6) /* Infra-Red mode */
#define ULCON_MASK	(ULCON_8BITS|ULCON_2STOP|ULCON_EVENPAR)

/* UCON bits - UART Control */
#define UCON_RXOFF	0x00
#define UCON_RXINT	0x01
#define UCON_RXDMA0	0x02 /* receiver uses DMA channel 0 */
#define UCON_RXDMA1	0x03 /* receiver uses DMA channel 1 */
#define UCON_TXOFF	0x00
#define UCON_TXINT	(1 << 2)
#define UCON_TXDMA0	(2 << 2) /* transmitter uses DMA channel 0 */
#define UCON_TXDMA1	(3 << 2) /* transmitter uses DMA channel 1 */
#define UCON_NOBRK	0x00
#define UCON_TXBRK	(1 << 4) /* send a break */
#define UCON_NOLOOP	0x00
#define UCON_LOOP	(1 << 5)
#define UCON_NOERRINT	0x00
#define UCON_ERRINT	(1 << 6)
#define UCON_NORXTO	0x00
#define UCON_RXTO	(1 << 7) /* RX interrupt after timeout - only w/FIFO */
#define UCON_PULSERXINT	0x00 /* RX interrupt as soon as a char arrives */
#define UCON_LEVELRXINT	(1 << 8) /* RX interrupt while a char arrives */
#define UCON_PULSETXINT	0x00 /* TX interrupt as soon as TX buffer is empty */
#define UCON_LEVELTXINT	(1 << 9) /* TX interrupt while TX buffer is empty */

/* UFCON bits - FIFO control */
#define UFCON_NOFIFO	0x00
#define UFCON_FIFO	0x01
#define UFCON_RXFIFORESET (1 << 1)
#define UFCON_TXFIFORESET (1 << 2)
#define UFCON_RXFIFOTL4	  0x00 /* interrupt after 4 bytes received */
#define UFCON_RXFIFOTL8	  (1 << 4) /* interrupt after 8 bytes received */
#define UFCON_RXFIFOTL12  (2 << 4) /* interrupt after 12 bytes received */
#define UFCON_RXFIFOTL16  (3 << 4) /* interrupt after 16 bytes received */
#define UFCON_TXFIFOTL0	  0x00 /* interrupt when 0 bytes are in the FIFO */
#define UFCON_TXFIFOTL4   (1 << 6) /* int. when 4 bytes are left in FIFO */
#define UFCON_TXFIFOTL8  (2 << 6) /* int. when 8 bytes are left in FIFO */
#define UFCON_TXFIFOTL12  (3 << 6) /* int. when 12 bytes are left in FIFO */

/* UMCON bits - MODEM control */
#define UMCON_RTSOFF	0x00 /* RTS SW control when AFC is off */
#define UMCON_RTSON	0x01 /* RTS SW control when AFC is off */
#define UMCON_AFCOFF	0x00
#define UMCON_AFCON	(1 << 4) /* RTS/CTS Automatic Flow Control in HW */

/* UTRSTAT bits - TX/RX status, use only witout FIFO */
#define UTRSTAT_RXDATA	0x01
#define UTRSTAT_TXBMPTY	0x02 /* TX buffer is empty */
#define UTRSTAT_TXBSMPTY 0x04 /* TX buffer AND shift register are empty */

/* UERSTAT bits - error bits */
#define UERSTAT_OVERRUN	0x01
#define UERSTAT_PARERR	0x02
#define UERSTAT_FRAERR	0x04
#define UERSTAT_BREAK	0x08
#define UERSTAT_ANY	0x0f

/* UFSTAT bits - FIFO status */
#define UFSTAT_RXCNTMASK	0x0f /* RX FIFO count mask */
#define UFSTAT_TXCNTMASK	0xf0 /* TX FIFO count mask */
#define UFSTAT_RXFIFOFULL	(1 << 8)
#define UFSTAT_TXFIFOFULL	(1 << 9)

/* UMSTAT bits MODEM status */
#define UMSTAT_CTSACTIVE	0x01 /* CTS is now active */
#define UMSTAT_CTSDELTA		0x04 /* CTS changed since the last check */

/* by chc, for S3C2400 */

/*
 * pending bit
 *
 */

#define BIT_EINT0	( 0x1 )
#define BIT_EINT1	( 0x1 << 1 )
#define BIT_EINT2	( 0x1 << 2 )
#define BIT_EINT3	( 0x1 << 3 )
#define BIT_EINT4	( 0x1 << 4 )
#define BIT_EINT5	( 0x1 << 5 )
#define BIT_EINT6	( 0x1 << 6 )
#define BIT_EINT7	( 0x1 << 7 )
#define BIT_TICK	( 0x1 << 8 )
#define BIT_WDT 	( 0x1 << 9 )
#define BIT_TIMER0	( 0x1 << 10 )
#define BIT_TIMER1	( 0x1 << 11 )
#define BIT_TIMER2	( 0x1 << 12 )
#define BIT_TIMER3	( 0x1 << 12 )
#define BIT_TIMER4	( 0x1 << 14 )
#define BIT_UERR01	( 0x1 << 15 )
#define BIT_NOTUSED	( 0x1 << 16 )
#define BIT_DMA0	( 0x1 << 17 )
#define BIT_DMA1	( 0x1 << 18 )
#define BIT_DMA2	( 0x1 << 19 )
#define BIT_DMA3	( 0x1 << 20 )
#define BIT_MMC 	( 0x1 << 21 )
#define BIT_SPI 	( 0x1 << 22 )
#define BIT_URXD0	( 0x1 << 23 )
#define BIT_URXD1	( 0x1 << 24 )
#define BIT_USBD	( 0x1 << 25 )
#define BIT_USBH	( 0x1 << 26 )
#define BIT_IIC 	( 0x1 << 27 )
#define BIT_UTXD0 	( 0x1 << 28 )
#define BIT_UTXD1 	( 0x1 << 29 )
#define BIT_RTC 	( 0x1 << 30 )
#define BIT_ADC 	( 0x1 << 31 )
#define BIT_ALLMSK 	( 0xffffffff )


/* 
 * Pulse Width Modulation (PWM) timer
 * 
 *
 * Registers
 *
 * 	rTCFG0		Configures the two 8-bit prescalers
 *			{prescaler value} = 0~255
 *			{divider value} = 2, 4, 8, 16, TCLKn
 *	rTCFG1		5-MUX & DMA mode selection register
 *	rTCON		Timer control register
 *	rTCONB4		Timer 4 count buffer register
 *	
 */    


#define	PWMTIMERBASE	0xf5100000	/* it's virtual address, physical : 0x1510 0000 */
#define	TCFG0		0x0		/* Timer Configuration 0, two 8-bit prescalers */
#define TCFG1		0x4		/* Timer Configuration 1, 5-MUX & DMA mode selection register */
#define TCON		0x8		/* Timer control register */
#define TCNTB0		0xc		/* Timer 0 count buffer register */
#define TCMPB0		0x10		/* Timer 0 compare buffer register */
#define TCNTO0		0x14		/* Timer 0 count observation register */
#define TCNTB1		0x18		/* Timer 1 */	
#define TCMPB1		0x1c
#define TCNTO1		0x20
#define TCNTB2		0x24		/* Timer 2 */
#define TCMPB2		0x28
#define TCNTO2		0x2c
#define TCNTB3		0x30		/* Timer 3 */
#define TCMPB3		0x34
#define TCNTO3		0x38
#define TCNTB4		0x3c		/* Timer 4 count buffer register */
#define TCNTO4		0x40		/* Timer 4 count observation register */

#define rTCFG0		*(volatile unsigned long *)(PWMTIMERBASE + TCFG0)
#define rTCFG1		*(volatile unsigned long *)(PWMTIMERBASE + TCFG1)
#define rTCON		*(volatile unsigned long *)(PWMTIMERBASE + TCON)
#define rTCNTB0		*(volatile unsigned long *)(PWMTIMERBASE + TCNTB0)
#define rTCMPB0		*(volatile unsigned long *)(PWMTIMERBASE + TCMPB0)
#define rTCNTO0		*(volatile unsigned long *)(PWMTIMERBASE + TCNTO0)
#define rTCNTB1		*(volatile unsigned long *)(PWMTIMERBASE + TCNTB1)
#define rTCMPB1		*(volatile unsigned long *)(PWMTIMERBASE + TCMPB1)
#define rTCNTO1		*(volatile unsigned long *)(PWMTIMERBASE + TCNTO1)
#define rTCNTB2		*(volatile unsigned long *)(PWMTIMERBASE + TCNTB2)
#define rTCMPB2		*(volatile unsigned long *)(PWMTIMERBASE + TCMPB2)
#define rTCNTO2		*(volatile unsigned long *)(PWMTIMERBASE + TCNTO2)
#define rTCNTB3		*(volatile unsigned long *)(PWMTIMERBASE + TCNTB3)
#define rTCMPB3		*(volatile unsigned long *)(PWMTIMERBASE + TCMPB3)
#define rTCNTO3		*(volatile unsigned long *)(PWMTIMERBASE + TCNTO3)
#define rTCNTB4		*(volatile unsigned long *)(PWMTIMERBASE + TCNTB4)
#define rTCNTO4		*(volatile unsigned long *)(PWMTIMERBASE + TCNTO4)


/*
 * Watchdog Timer
 *
 *
 * Registers
 *
 *  rWTCON  	WDT control register
 *	   - WDTEN, WDTINTEN, WDTRSTEN
 *  rWTDAT  	WDT data register
 *  rWTCNT  	WDT count register
 */

#define WDTBASE		0xf5300000  /* 0x15300000 physical */
#define WTCON		0x0
#define WTDAT		0x4
#define WTCNT		0x8

#define rWTCON		*(volatile unsigned short *)(WDTBASE + WTCON)
#define WDTEN		0x20
#define WDTINTEN	0x40
#define WDTRSTEN	0x1

#define rWTDAT		*(volatile unsigned short *)(WDTBASE + WTDAT)
#define rWTCNT		*(volatile unsigned short *)(WDTBASE + WTCNT)


/* 
 * Real Time Clock (RTC) 
 * 
 *
 * Registers
 *
 * 	rRTCCON		RTC control register 
 *			- RTCEN, CLKSEL, CNTSEL, CLKRST
 *	rTICCNT		Tick time counter register
 *	rRTCALM		RTC alarm control register
 *	rALMSEC		Alarm second data register
 *	rALMMIN		Alarm miinute data register
 *	rALMHOUR	Alarm hour data register
 *	rALMDAY		Alarm day data register
 *	rALMMON		Alarm month data register
 *	rALMYEAR	Alarm year data register
 *	rRTCRST		RTC round reset register
 *	rBCDSEC		BCD second register
 *	rBCDMIN		BCD minute register
 *	rBCDHOUR	BCD hour register
 *	rBCDDAY		BCD day register
 *	rBCDDATE	BCD data register
 *	rBCDMON		BCD mon register
 *	rBCDYEAR	BCD year register
 *	
 */    

    
    
#define	RTCBASE		0xf5700000	/* it's virtual address, physical : 0x1570 0000 */
#define	RTCCON		0x40		/* RTC control register */
#define TICNT		0x44		/* Tick time counter register */
#define RTCALM		0x50		/* RTC alarm control register */
#define ALMSEC		0x54		/* alarm second data register */
#define ALMMIN		0x58		/* alarm minute data register */
#define ALMHOUR		0x5c		/* alarm hour data register */
#define ALMDAY		0x60		/* alarm day data register */
#define ALMMON		0x64		/* alarm month data register */
#define ALMYEAR		0x68		/* alarm year data register */
#define RTCRST		0x6c		/* RTC round reset register */
#define BCDSEC		0x70		/* BCD second regiser */
#define BCDMIN		0x74		/* BCD minute register */
#define BCDHOUR		0x78		/* BCD hour register */
#define BCDDAY		0x7c		/* BCD day register */
#define BCDDATE		0x80		/* BCD data register */
#define BCDMON		0x84		/* BCD month register */
#define BCDYEAR		0x88		/* BCD year register */

/* the handbook shows these as character wide registers ! */
#define rRTCCON		*(volatile unsigned char *)(RTCBASE + RTCCON)
#define rTICNT		*(volatile unsigned char *)(RTCBASE + TICNT)
#define rRTCALM		*(volatile unsigned char *)(RTCBASE + RTCALM)
#define rALMSEC		*(volatile unsigned char *)(RTCBASE + ALMSEC)
#define rALMMIN		*(volatile unsigned char *)(RTCBASE + ALMMIN)
#define rALMHOUR	*(volatile unsigned char *)(RTCBASE + ALMHOUR)
#define rALMDAY		*(volatile unsigned char *)(RTCBASE + ALMDAY)
#define rALMMON		*(volatile unsigned char *)(RTCBASE + ALMMON)
#define rALMYEAR	*(volatile unsigned char *)(RTCBASE + ALMYEAR)
#define rRTCRST 	*(volatile unsigned char *)(RTCBASE + RTCRST)
#define rBCDSEC 	*(volatile unsigned char *)(RTCBASE + BCDSEC)
#define rBCDMIN 	*(volatile unsigned char *)(RTCBASE + BCDMIN)
#define rBCDHOUR 	*(volatile unsigned char *)(RTCBASE + BCDHOUR)
#define rBCDDAY 	*(volatile unsigned char *)(RTCBASE + BCDDAY)
#define rBCDDATE 	*(volatile unsigned char *)(RTCBASE + BCDDATE)
#define rBCDMON 	*(volatile unsigned char *)(RTCBASE + BCDMON)
#define rBCDYEAR 	*(volatile unsigned char *)(RTCBASE + BCDYEAR)



/* by chc, S3C2400 */

/*
 * Interrupt Controller (IC) control registers
 *
 * Registers
 *
 *    rSRCPND		Interrupt request status (read/write).
 *			0 = the interrupt has not been requested
 *			1 = the interrupt source has asserted the interrupt request
 *			When the user clear a interrupt pending, specific bit of SRCPND, has to clear the bit of SRCPND.
 *			Note that each bit of SRCPND register is automatically set by the interruptsources regardless of the masking bits in the INT MASK register. In addition, it is not affected by the priority logic of interrupt controller.
 *    rINTMOD		Interrupt mode register (write).
 *			0 = IRQ mode, 1 = FIQ mode
 *    rINTMSK		Interrupt mask register (read/write). The masked interrupt source will not be serviced.
 *			0 = interrupt service is available
 * 			1 = interrupt service is masked
 *    rPRIORITY		IRQ priority control register (write).
 *    rINTPND		Interrupt pending register (read/write). Since INTPND is located affter the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating IRQ to CPU. In interrupt service routine for IRQ, you can read this register to determine the interrupt source to be serviced among 32 sources. This register has to be cleared in the interrupt service routine AFTER cleaning SRCPND register. We can clear a specific bit of INTPND register by writing a data to this register.
 *			0 = the interrupt has not been requested
 *			1 = the interrupt source has asserted the interrupt request
 *    rINTOFFSET		the IRQ interrupt request source (read).
 *			indicate which interrupt request of IRQ mode is in the INTPND register.
 */

#define	INTBASE		0xf4400000	/* it's virtual address, physical : 0x1440 0000 */
#define	SRCPND		0x0	/* source pending register */
#define INTMOD		0x4	/* interrupt mode register */
#define INTMSK		0x8	/* interrupt mask register */
#define PRIORITY	0xc	/* priority register */
#define	INTPND		0x10	/* interrupt pending register */
#define INTOFFSET	0x14	/* interrupt offset register */

#define rSRCPND		*(volatile unsigned long *)(INTBASE + SRCPND)
#define rINTMOD		*(volatile unsigned long *)(INTBASE + INTMOD)
#define rINTMSK		*(volatile unsigned long *)(INTBASE + INTMSK)
#define rPRIORITY	*(volatile unsigned long *)(INTBASE + PRIORITY)
#define rINTPND		*(volatile unsigned long *)(INTBASE + INTPND)
#define rINTOFFSET	*(volatile unsigned long *)(INTBASE + INTOFFSET)


/* added by chc, for LCD, S3C2400 */
/*
 * Liquid Crystal Display (LCD) control registers
 *
 * Registers
 *
 *    LCDCON1     	Liquid Crystal Display (LCD) Control Register 1
 *              	(read/write).
 *    LCDCON2     	Liquid Crystal Display (LCD) Control Register 2
 *              	(read/write).
 *    LCDCON3     	Liquid Crystal Display (LCD) Control Register 3
 *          	   	(read/write).
 *    LCDCON4     	Liquid Crystal Display (LCD) Control Register 4
 *              	(read/write).
 *    LCDCON5     	Liquid Crystal Display (LCD) Control Register 5
 *              	(read/write).
 *    LCDSADDR1      	Frame Buffer Start Address Register 1
 *              	(read/write).
 *    LCDSADDR2      	Frame Buffer Start Address Register 2
 *              	(read/write).
 *    LCDSADDR3      	Frame Buffer Start Address Register 3
 *              	(read/write).
 *    REDLUT      	RED Lookup Table Register
 *              	(read/write).
 *    GREENLUT      	GREEN Lookup Table Register
 *              	(read/write).
 *    BLUELUT      	BLUE Lookup Table Register
 *              	(read/write).
 *    DP1_2		Dithering Pattern DP1_2 Register
 *              	(read/write).
 *    DP4_7		Dithering Pattern DP4_7 Register
 *              	(read/write).
 *    DP3_5		Dithering Pattern DP3_5 Register
 *              	(read/write).
 *    DP2_3		Dithering Pattern DP2_3 Register
 *              	(read/write).
 *    DP5_7		Dithering Pattern DP5_7 Register
 *              	(read/write).
 *    DP3_4		Dithering Pattern DP3_4 Register
 *              	(read/write).
 *    DP4_5		Dithering Pattern DP4_5 Register
 *              	(read/write).
 *    DP6_7		Dithering Pattern DP6_7 Register
 *              	(read/write).
 *    DITHMODE		Dithering Mode Register
 *              	(read/write).
 *    TPAL		Temp Palette Register
 *              	(read/write).
 *    PALETTE		user global varible
 */
#define LCDBASE		0xf4a00000

#define rLCDCON1	(*(volatile unsigned long*)(LCDBASE+0x00))
#define rLCDCON2	(*(volatile unsigned long*)(LCDBASE+0x04))
#define rLCDCON3	(*(volatile unsigned long*)(LCDBASE+0x08))
#define rLCDCON4	(*(volatile unsigned long*)(LCDBASE+0x0c))
#define rLCDCON5	(*(volatile unsigned long*)(LCDBASE+0x10))
#define rLCDSADDR1	(*(volatile unsigned long*)(LCDBASE+0x14))
#define rLCDSADDR2	(*(volatile unsigned long*)(LCDBASE+0x18))
#define rLCDSADDR3	(*(volatile unsigned long*)(LCDBASE+0x1c))
#define rREDLUT		(*(volatile unsigned long*)(LCDBASE+0x20))
#define rGREENLUT	(*(volatile unsigned long*)(LCDBASE+0x24))
#define rBLUELUT	(*(volatile unsigned long*)(LCDBASE+0x28))
#define rDP1_2		(*(volatile unsigned long*)(LCDBASE+0x2c))
#define rDP4_7		(*(volatile unsigned long*)(LCDBASE+0x30))
#define rDP3_5		(*(volatile unsigned long*)(LCDBASE+0x34))
#define rDP2_3		(*(volatile unsigned long*)(LCDBASE+0x38))
#define rDP5_7		(*(volatile unsigned long*)(LCDBASE+0x3c))
#define rDP3_4		(*(volatile unsigned long*)(LCDBASE+0x40))
#define rDP4_5		(*(volatile unsigned long*)(LCDBASE+0x44))
#define rDP6_7		(*(volatile unsigned long*)(LCDBASE+0x48))
#define rDITHMODE	(*(volatile unsigned long*)(LCDBASE+0x4c))
#define rTPAL		(*(volatile unsigned long*)(LCDBASE+0x50))

/* end of LCD by chc */
/* I/O ports */
/*
 * I/O ports
 * PACON	Port A control register
 *		(read/write)
 * PADAT	Port A data register
 *		(read/write)
 * PBCON	Port B control register
 *		(read/write)
 * PBDAT	Port B data register
 *		(read/write)
 * PBUP		Port B pull-up disable register
 *		(read/write)
 * PCCON	Port C control register
 *		(read/write)
 * PCDAT	Port C data register
 *		(read/write)
 * PCUP		Port C pull-up disable register
 *		(read/write)
 * PDCON	Port D control register
 *		(read/write)
 * PDDAT	Port D data register
 *		(read/write)
 * PDUP		Port D pull-up disable register
 *		(read/write)
 *	...
 */

#define IOPORTBASE	0xf5600000 
/* I/O PORT */ 
#define rPACON		(*(volatile unsigned long*)(IOPORTBASE+0x00))
#define rPADAT		(*(volatile unsigned long*)(IOPORTBASE+0x04))
                	
#define rPBCON		(*(volatile unsigned long*)(IOPORTBASE+0x08))
#define rPBDAT		(*(volatile unsigned long*)(IOPORTBASE+0x0c))
#define rPBUP		(*(volatile unsigned long*)(IOPORTBASE+0x10))
                	
#define rPCCON		(*(volatile unsigned long*)(IOPORTBASE+0x14))
#define rPCDAT		(*(volatile unsigned long*)(IOPORTBASE+0x18))
#define rPCUP		(*(volatile unsigned long*)(IOPORTBASE+0x1c))
                	
#define rPDCON		(*(volatile unsigned long*)(IOPORTBASE+0x20))
#define rPDDAT		(*(volatile unsigned long*)(IOPORTBASE+0x24))
#define rPDUP		(*(volatile unsigned long*)(IOPORTBASE+0x28))
                	
#define rPECON		(*(volatile unsigned long*)(IOPORTBASE+0x2c))
#define rPEDAT		(*(volatile unsigned long*)(IOPORTBASE+0x30))
#define rPEUP		(*(volatile unsigned long*)(IOPORTBASE+0x34))
                	
#define rPFCON		(*(volatile unsigned long*)(IOPORTBASE+0x38))
#define rPFDAT		(*(volatile unsigned long*)(IOPORTBASE+0x3c))
#define rPFUP		(*(volatile unsigned long*)(IOPORTBASE+0x40))
                	
#define rPGCON		(*(volatile unsigned long*)(IOPORTBASE+0x44))
#define rPGDAT		(*(volatile unsigned long*)(IOPORTBASE+0x48))
#define rPGUP		(*(volatile unsigned long*)(IOPORTBASE+0x4c))
                	
#define rOPENCR		(*(volatile unsigned long*)(IOPORTBASE+0x50))
#define rMISCCR		(*(volatile unsigned long*)(IOPORTBASE+0x54))
#define rEXTINT		(*(volatile unsigned long*)(IOPORTBASE+0x58))

/* ADC interface */
/* S3C2400X01 Ananlog-to-Digital Converter registers
 * Registers
 * ADCCON		ADC Control Register
 *			(read/write)
 * ADCDAT		ADC DATA Register
 *			(read)
 */

#define ADCBASE 0xf5800000
#define rADCCON		(*(volatile unsigned short *)(ADCBASE + 0x00))
#define rADCDAT		(*(volatile unsigned short *)(ADCBASE + 0x04))

/* Bit definitions for ADCCON */
#define ADC_ENABLE_START     0x1
#define ADC_READ_START       0x2
#define ADC_STDBM            0x4
#define ADC_INP_AIN0         (0x0 << 3)
#define ADC_INP_AIN1         (0x1 << 3)
#define ADC_INP_AIN2         (0x2 << 3)
#define ADC_INP_AIN3         (0x3 << 3)
#define ADC_INP_AIN4         (0x4 << 3)
#define ADC_INP_AIN5         (0x5 << 3)
#define ADC_INP_AIN6         (0x6 << 3)
#define ADC_INP_AIN7         (0x7 << 3)
#define ADC_PRSCEN           0x4000
#define ADC_ECFLG            0x8000

/* SPI interface */
/* S3C2400X01 Serial Peripheral Interface control registers 
 * Registers
 * SPCON		Serial Peripheral Interface(SPI) Control Register
 *			(read/write)
 * SPSTA		SPI Status Register
 *			(read)
 * SPPIN		SPI Pin Control Register
 *			(read/write)
 * SPPRE		SPI Baud Rate Prescaler Register
 *			(read/write)
 * SPTDAT		SPI Tx Data Register
 *			(read/write)
 * SPRDAT		SPI Rx Data Register
 *			(read)
 *
 */
 
#define SPIBASE	0xf5900000
/* SPI registers */
#define rSPCON		(*(volatile unsigned long *)(SPIBASE + 0x00))
#define rSPSTA		(*(volatile unsigned long *)(SPIBASE + 0x04))
#define rSPPIN		(*(volatile unsigned long *)(SPIBASE + 0x08))
#define rSPPRE		(*(volatile unsigned long *)(SPIBASE + 0x0c))
#define rSPTDAT		(*(volatile unsigned long *)(SPIBASE + 0x10))
#define rSPRDAT		(*(volatile unsigned long *)(SPIBASE + 0x14))

/* Clock & Power Management */
/*
 * Registers
 *
 * LOCKTIME		PLL lock time count register
 *			(read/write)
 * MPLLCON		MPLL configuration register
 *			(read/write)
 * UPLLCON		UPLL configuration register
 *			(read/write)
 * CLKCON		Clock generator control register
 *			(read/write)
 * CLKSLOW		Slow clock control register
 *			(read/write)
 * CLKDIVN		Clock divider control register
 *			(read/write)
 */

#define CLKBASE		0xf4800000
#define rLOCKTIME	(*(volatile unsigned long *)(CLKBASE + 0x00))
#define rMPLLCON	(*(volatile unsigned long *)(CLKBASE + 0x04))
#define rUPLLCON	(*(volatile unsigned long *)(CLKBASE + 0x08))
#define rCLKCON		(*(volatile unsigned long *)(CLKBASE + 0x0c))
#define rCLKSLOW	(*(volatile unsigned long *)(CLKBASE + 0x10))
#define rCLKDIVN	(*(volatile unsigned long *)(CLKBASE + 0x14))

/* CLKCON bits */
#define CLKCON_STOP	(1 << 0)
#define CLKCON_SL_IDLE	(1 << 1)
#define CLKCON_IDLE	(1 << 2)
#define CLKCON_LCDC	(1 << 3)
#define CLKCON_USBH	(1 << 4)
#define CLKCON_USBD	(1 << 5)
#define CLKCON_TIMER	(1 << 6)
#define CLKCON_MMC	(1 << 7)
#define CLKCON_UART0	(1 << 8)
#define CLKCON_UART1	(1 << 9)
#define CLKCON_GPIO	(1 << 10)
#define CLKCON_RTC	(1 << 11)
#define CLKCON_ADC	(1 << 12)
#define CLKCON_I2C	(1 << 13)
#define CLKCON_I2S	(1 << 14)
#define CLKCON_SPI	(1 << 15)

/* USB Host Interface (OHCI 1.0 compatible) */
#define USBHOSTBASE	0xf4200000
#define USBHOSTSIZE	0x60

#undef C
#undef Assembly

